SI3021 datasheet(20/54 Pages) ETC

20 / 54 page

Si 30 35

Rev. 1.2

The digital interface consists of a single, synchronous

serial link which communicates both telephony and

control data.

In Serial mode 0 or 1, the Si3021 operates as a master,

where the master clock (MCLK) is an input, the serial

data clock (SCLK) is an output, and the frame sync

signal (FSYNC) is an output. The MCLK frequency and

the value of the sample rate control registers 7, 8, 9,

and 10 determine the sample rate (Fs). The serial port

clock, SCLK, runs at 256 bits per frame, where the

frame rate is equivalent to the sample rate. Refer to

"Clock Generation Subsystem" on page 20 for more

details on programming sample rates.

The Si3035 transfers 16-bit or 15-bit telephony data in

the primary timeslot and 16-bit control data in the

secondary timeslot. Figure 19 and Figure 20 show the

relative timing of the serial frames. Primary frames

occur at the frame rate and are always present. To

minimize overhead in the external DSP, secondary

frames are present only when requested.

Two methods exist for transferring control information in

the secondary frame. The default power-up mode uses

the LSB of the 16-bit transmit (TX) data word as a flag

to request a secondary transfer. In this mode, only

15-bit TX data is transferred, resulting in a loss of SNR

but allowing software control of the secondary frames.

As an alternative method, the FC pin can serve as a

hardware flag for requesting a secondary frame. The

external DSP can turn on the 16-bit TX mode by setting

the SB bit of Register 1. In the 16-bit TX mode, the

hardware FC pin must be used to request secondary

transfers.

Figure 21 and Figure 22 illustrate the secondary frame

read cycle and write cycle, respectively. During a read

cycle, the R/W bit is high and the 5-bit address field

contains the address of the register to be read. The

contents of the 8-bit control register are placed on the

SDO signal. During a write cycle, the R/W bit is low and

the 5-bit address field contains the address of the

immediately follows the address on SDI. Only one

frame. See "Control Registers" on page 34 for the

In serial mode 2, the Si3021 operates as a slave device,

where the MCLK is an input, the SCLK is a no connect

(except for the master device for which it is an output),

and the FSYNC is an input. In addition, the RGDT/FSD

pin operates as a delayed frame sync (FSD) and the

FC/RGDT pin operates as ring detect (RGDT). In this

mode, FC operation is not supported. For further details

on operating the Si3021 as a slave device, refer to

"Multiple Device Support" on page 25.

Clock Generation Subsystem

The Si3035 contains an on-chip clock generator. Using

a single MCLK input frequency, the Si3035 can

generate all the desired standard modem sample rates,

as well as the common 11.025 kHz rate for audio

playback.

The clock generator consists of two PLLs (PLL1 and

PLL2) that achieve the desired sample frequencies.

Figure 23 on page 22 illustrates the clock generator.

Figure 19. Software FC Secondary Request

Com m unications Fram e 1 (CF1)

(CF2)

16 S C LK S

128 S C LK S

256 S C LK S

Prim ary

FSYN C

XMT D ata

S econdary

Data

XMT D ata

SD I

RCV Data

S econdary

Data

RCV Data

SD O

D 15 – D 1

D 0 = 1 (S oftware F C Bit)

S e condary

P rim ary

D 15 – D 1

D 0 = 0 (S oftware F C Bit)

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