SI3021 datasheet(10/54 Pages) ETC

10 / 54 page

Si 30 35

Rev. 1.2

Figure 5. Serial Interface Timing Diagram (DCE = 1, FSD = 1)

Table 10. Switching Characteristics—Serial Interface (DCE = 1, FSD = 1)

(VA = Charge Pump, VD = 3.0 to 5.25 V, TA = 0 to 70°C for K-Grade, CL = 20 pF)

Parameter1,2

Symbol

Min

Typ

Max

Unit

Cycle Time, SCLK

354

1/256 Fs

—

SCLK Duty Cycle

tdty

—50

—

Delay Time, SCLK

↑ to FSYNC ↑

td1

—

Delay Time, SCLK

↑ to FSYNC ↓

td2

—

Delay Time, SCLK

↑ to SDO valid

td3

0.25tc – 20

—

0.25tc + 20

Delay Time, SCLK

↑ to SDO Hi-Z

td4

—

Delay Time, SCLK

↑ to RGDT ↓

td5

—

Setup Time, SDO Before SCLK

↓

tsu

—

Hold Time, SDO After SCLK

↓

—

Setup Time, SDI Before SCLK

tsu2

—

Hold Time, SDI After SCLK

th2

—

Notes:

1. All timing is referenced to the 50% level of the waveform. Input test levels are VIH = VD – 0.4 V, VIL = 0.4 V.

2. Refer to the section "Multiple Device Support" on page 25 for functional details.

D15

SCLK

FSYNC

(m ode 1)

SDO

(m aster)

FSD

SDI

SDO

(slave 1)

D14

D15

D14

D13

D15

su2

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