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PM6341 Datasheet(PDF) 4 Page - PMC-Sierra, Inc |
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PM6341 Datasheet(HTML) 4 Page - PMC-Sierra, Inc |
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4 / 272 page ![]() PM6341 E1XC DATA SHEET PMC-910419 ISSUE 8 E1 FRAMER/TRANSCEIVER PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ii 1.9 BACKPLANE RECEIVE INTERFACE (BRIF) .............................. 53 1.10 TRANSMITTER (TRAN) .............................................................. 53 1.11 TRANSMIT PER-CHANNEL SERIAL CONTROLLER (TPSC) .... 54 1.12 HDLC TRANSMITTER (XFDL) .................................................... 54 1.13 DIGITAL JITTER ATTENUATOR (DJAT)....................................... 55 1.14 TIMING OPTIONS (TOPS) .......................................................... 59 1.15 DIGITAL DS-1 TRANSMIT INTERFACE (DTIF) ........................... 60 1.16 ANALOG PULSE GENERATOR (XPLS)...................................... 60 1.17 BACKPLANE TRANSMIT INTERFACE (BTIF) ............................ 62 1.18 MICROPROCESSOR INTERFACE (MPIF) ................................. 62 10 REGISTER DESCRIPTION.................................................................... 63 11 NORMAL MODE REGISTER DESCRIPTION........................................ 66 11.1 INTERNAL REGISTERS ............................................................. 67 1.1.1 REGISTERS 49-4FH: LATCHING PERFORMANCE DATA ........................................................................................ 177 12 TEST FEATURES DESCRIPTION ....................................................... 187 12.1 INTERNAL REGISTERS ........................................................... 190 12.2 TEST MODE 0 ........................................................................... 191 13 TIMING DIAGRAMS ............................................................................. 193 14 OPERATIONS....................................................................................... 198 14.1 CONFIGURING THE E1XC FROM RESET............................... 198 14.2 USING THE INTERNAL FDL TRANSMITTER ........................... 199 14.3 USING THE INTERNAL FDL RECEIVER.................................. 201 14.3.1 KEY USED ON SUBSEQUENT DIAGRAMS: ................. 205 |
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