PM6341 datasheet(17/272 Pages) PMC

17 / 272 page

PM6341 E1XC

DATA SHEET

PMC-910419

ISSUE 8

E1 FRAMER/TRANSCEIVER

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE

FEATURES

• Integrates a full-featured E1 transceiver in a single device with analog

circuitry for receiving and transmitting G.703 2048 kbit/s compatible signals

and digital circuitry for terminating the duplex digital signal.

• Pin compatible with the PMC PM4341A T1 Framer/Transceiver device.

• Provides an 8-bit microprocessor bus interface for configuration, control, and

status monitoring.

• Low power CMOS technology.

• Available in either a 68 pin PLCC or an 80 pin PQFP package.

The receiver section:

• Provides analog circuitry for receiving a G.703 2048 kbit/s signal with up to 6

dB of cable attenuation. Direct digital inputs are also provided to allow for by-

passing the analog front-end.

• Recovers clock and data using a digital phase locked loop for high jitter

tolerance. A direct clock input is provided to allow clock recovery to be by-

passed.

• Accepts dual rail or single rail digital PCM inputs.

• Supports HDB3 or AMI line code.

• Accepts gapped data streams to support higher rate demultiplexing.

• Frames to a G.704 2048 kbit/s signal within 1 ms.

• Frames to the signalling multiframe alignment when enabled.

• Frames to the CRC multiframe alignment when enabled.

• Provides loss of signal detection, and indicates loss of frame alignment

(OOF), loss of signalling multiframe alignment and loss of CRC multiframe

alignment.

• Supports line and path performance monitoring according to ITU-T

recommendations. Accumulators are provided for counting:

• CRC-4 errors to 1000 per second;

• Far end block errors to 1000 per second;

• Frame sync errors to 127 per second; and

• Line code violations to 8191 per second.

PM6341 Datasheet(PDF) 17 Page - PMC-Sierra, Inc