PM6341 datasheet(70/272 Pages) PMC

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PM6341 E1XC

DATA SHEET

PMC-910419

ISSUE 8

E1 FRAMER/TRANSCEIVER

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE

If there are more than five consecutive ones in the raw transmit data or in the

CRC data, a zero is stuffed into the serial data output. This prevents the

unintentional transmission of flag or abort characters.

Abort characters can be continuously transmitted at any time by setting a control

bit. During transmission, an underrun situation can occur if data is not written to

the Transmit Data Register before the previous byte has been depleted. In this

case, an abort sequence is transmitted, and the controlling processor is notified

via the TDLUDR signal. Optionally, the interrupt and underrun signals can be

independently enabled to also generate an interrupt on the INTB output,

providing a means to notify the controlling processor of changes in the XFDL

operating status.

When the internal HDLC transmitter is disabled, the serial data to be transmitted

on data link can be input on the TDLSIG pin timed to the clock rate output on the

TDLCLK pin.

9.13

Digital Jitter Attenuator (DJAT)

The Digital Jitter Attenuation function is provided by the Digital Jitter Attenuator

(DJAT) block. The DJAT block receives jittered, dual-rail E1 data in NRZ format

from TRAN on two separate inputs, which allows bipolar violations to pass

through the block uncorrected. The incoming data streams are stored in a FIFO

timed to the transmit clock (either BTCLK or RCLKO). The respective input data

emerges from the FIFO timed to the jitter attenuated clock (TCLKO) referenced

to either TCLKI, BTCLK, or RCLKO.

The jitter attenuator generates the jitter-free 2.048 MHz TCLKO output transmit

clock by adaptively dividing the 49.152 MHz XCLK signal according to the phase

difference between the generated TCLKO and input data clock to DJAT (either

BTCLK or RCLKO). Jittered fluctuations in the phase of the input data clock are

attenuated by the phase-locked loop within DJAT so that the frequency of TCLKO

is equal to the average frequency of the input data clock. Phase fluctuations with

a jitter frequency above 8.8 Hz are attenuated by 6 dB per octave of jitter

frequency. Wandering phase fluctuations with frequencies below 8.8 Hz are

tracked by the generated TCLKO. To provide a smooth flow of data out of DJAT,

TCLKO is used to read data out of the FIFO.

If the FIFO read pointer (timed to TCLKO) comes within one bit of the write

pointer (timed to the input data clock, BTCLK or RCLKO), DJAT will track the jitter

of the input clock. This permits the phase jitter to pass through unattenuated,

inhibiting the loss of data.

PM6341 Datasheet(PDF) 70 Page - PMC-Sierra, Inc

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