PM6341 datasheet(82/272 Pages) PMC

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PM6341 E1XC

DATA SHEET

PMC-910419

ISSUE 8

E1 FRAMER/TRANSCEIVER

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE

11.1

Internal Registers

Bit

Type

Function

Default

Bit 7

R/W

WORDERR

Bit 6

R/W

CNTNFAS

Bit 5

R/W

ELSTBYP

Bit 4

R/W

TRSLIP

Bit 3

R/W

SRPCM

Bit 2

R/W

SRSMFP

Bit 1

R/W

SRCMFP

Bit 0

R/W

TRKEN

This register allows software to configure the receive functions of the E1XC.

WORDERR:

The WORDERR bit determines how frame alignment signal (FAS) errors are

reported. When WORDERR is logic 1, one or more errors in the seven bit

FAS word results in a single framing error count. When WORDERR is logic 0,

each error in a FAS word results in a single framing error count.

CNTNFAS:

When the CNTNFAS bit is a logic 1, a zero in bit 2 of time slot 0 of non-frame

alignment signal (NFAS) frames results in an increment of the framing error

count. If WORDERR is also a logic 1, the word is defined as the eight bits

comprising the FAS pattern and bit 2 of time slot 0 of the next NFAS frame.

When the CNTNFAS bit is a logic 0, only errors in the FAS affect the framing

error count.

ELSTBYP:

The ELSTBYP bit allows the Elastic Store (ELST) block to be bypassed,

eliminating the one frame delay incurred through the ELST. When set to logic

1, the received data and clock inputs to ELST are internally routed directly to

the ELST outputs.

TRSLIP:

The TRSLIP bit allows the ELST block to be used to measure, through SLIP

indications, the frequency difference between the recovered receive line clock

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