PM6341 datasheet(69/272 Pages) PMC

69 / 272 page

PM6341 E1XC

DATA SHEET

PMC-910419

ISSUE 8

E1 FRAMER/TRANSCEIVER

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE

output. Support is provided for the transmission of AIS and TS16 AIS, and the

transmission of remote alarm and remote multiframe alarm signals.

PCM output signals may be selected to conform to HDB3 or AMI line coding.

9.11

Transmit Per-channel Serial Controller (TPSC)

The Transmit Per-channel Serial Controller allows data and signalling trunk

conditioning or idle code to be applied on the transmit E-1 stream on a per-

timeslot basis. It also allows per-timeslot control of data inversion and application

of digital milliwatt.

The Transmit Per-channel Serial Controller function is provided by a Per-Channel

Serial Controller (PCSC) block. The TPSC interfaces directly to the TRAN block

and provides serial streams for signalling control, idle code data and PCM data

control.

The registers are accessible from the µP interface in an indirect address mode.

The BUSY indication signal can be polled from an internal status register to

check for completion of the current operation.

9.12

HDLC Transmitter (XFDL)

The HDLC Transmitter function is provided by the XFDL block. The XFDL is

designed to provide a serial data link for the TRAN E1 Transmitter block. The

XFDL is used under microprocessor or DMA control to transmit HDLC data

frames in Time Slot 16 or in the Time Slot 0 National Use bits when the E1XC is

enabled to use the internal HDLC transmitter. The XFDL performs all of the data

serialization, CRC generation, zero-bit stuffing, as well as flag, idle, and abort

sequence insertion. Data to be transmitted is provided on an interrupt-driven

basis by writing to a double-buffered transmit data register. Upon completion of

the frames, a CRC Q.921 frame check sequence is transmitted, followed by idle

flag sequences. If the transmit data register underflows, an abort sequence is

automatically transmitted.

When enabled for use (via the EN bit in the XFDL Configuration register), the

XFDL continuously transmits the flag character (01111110). Data bytes to be

transmitted are written into the Transmit Data Register. After the parallel-to-serial

conversion of each data byte, an interrupt is generated to signal the controller to

write the next byte into the Transmit Data Register. After the last data frame byte

is transmitted, the CRC word (if CRC insertion has been enabled), or a flag (if

CRC insertion has not been enabled) is transmitted. The XFDL then returns to

the transmission of flag characters.

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