PM6341 datasheet(12/272 Pages) PMC

12 / 272 page

PM6341 E1XC

DATA SHEET

PMC-910419

ISSUE 8

E1 FRAMER/TRANSCEIVER

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE

FIGURE 22- TYPICAL DATA FRAME.............................................................. 204

FIGURE 23- RFDL NORMAL DATA AND ABORT SEQUENCE...................... 205

FIGURE 24- RFDL FIFO OVERRUN .............................................................. 206

FIGURE 25- XFDL NORMAL DATA SEQUENCE ........................................... 207

FIGURE 26- XFDL UNDERRUN SEQUENCE ................................................ 208

FIGURE 27- PAYLOAD LOOPBACK............................................................... 209

FIGURE 28- LINE LOOPBACK....................................................................... 210

FIGURE 29- DIAGNOSTIC DIGITAL LOOPBACK .......................................... 211

FIGURE 30- DIAGNOSTIC METALLIC LOOPBACK....................................... 212

FIGURE 31- LONGITUDINALLY BALANCED RECEIVE LINE INTERFACE .. 219

FIGURE 32- CODE REGISTER SEQUENCE DURING G.803 (120

Ω) PULSE

GENERATION ...................................................................................... 223

FIGURE 33- LCV COUNT VS. BER ................................................................ 227

FIGURE 34- FER COUNT VS. BER ................................................................ 228

FIGURE 35- CRCE COUNT VS. BER ............................................................. 229

FIGURE 36- MICROPROCESSOR READ ACCESS TIMING ......................... 235

FIGURE 37- MICROPROCESSOR WRITE ACCESS TIMING ....................... 237

FIGURE 38- BACKPLANE TRANSMIT INPUT TIMING DIAGRAM ................ 239

FIGURE 39- XCLK=49.152MHZ INPUT TIMING ............................................ 240

FIGURE 40- TCLKI INPUT TIMING ................................................................ 242

FIGURE 41- DIGITAL RECEIVE INTERFACE INPUT TIMING DIAGRAM...... 243

FIGURE 42- TRANSMIT DATA LINK INPUT TIMING DIAGRAM .................... 244

FIGURE 43- BACKPLANE RECEIVE INPUT TIMING DIAGRAM................... 245

FIGURE 44- RECEIVE DATA LINK OUTPUT TIMING DIAGRAM................... 246

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