LAN89218 datasheet(106/148 Pages) MICROCHIP

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LAN89218

DS60001255B-page 106

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5.4.6

MII_ACC—MII ACCESS REGISTER

This register is used to control the Management cycles to the PHY.

5.4.7

MII_DATA—MII DATA REGISTER

This register contains either the data to be written to the PHY register specified in the MII Access Register, or the

read data from the PHY register whose index is specified in the MII Access Register.

Offset:

Attribute:

R/W

Default Value:

00000000h

Size:

32 bits

Bits

Description

31:16

Reserved

15:11

PHY Address: For every access to this register, this field must be set to 00001b.

10:6

MII Register Index (MIIRINDA): These bits select the desired MII register in the PHY.

5:2

Reserved

MII Write (MIIWnR): Setting this bit tells the PHY that this will be a write operation using the MII data

MII Busy (MIIBZY): This bit must be polled to determine when the MII register access is complete. This

bit must read a logical 0 before writing to this register and MII data register.

The LAN driver software must set (1) this bit in order for the LAN89218 to read or write any of the MII

PHY registers.

During a MII register access, this bit will be set, signifying a read or write access is in progress. The MII

data register must be kept valid until the MAC clears this bit during a PHY write operation. The MII data

Offset:

Attribute:

R/W

Default Value:

00000000h

Size:

32 bits

Bits

Description

31:16

Reserved

15:0

MII Data. This contains the 16-bit value read from the PHY read operation or the 16-bit data value to be

written to the PHY before an MII write operation.

LAN89218 Datasheet(PDF) 106 Page - Microchip Technology

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