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DM505 Datasheet(PDF) 97 Page - Texas Instruments |
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DM505 Datasheet(HTML) 97 Page - Texas Instruments |
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97 / 286 page ![]() 97 DM505 www.ti.com SPRS976A – NOVEMBER 2016 – REVISED JANUARY 2017 Submit Documentation Feedback Specifications Copyright © 2016–2017, Texas Instruments Incorporated 5.9 Timing Requirements and Switching Characteristics 5.9.1 Timing Parameters and Information The timing parameter symbols used in the timing requirement and switching characteristic tables are created in accordance with JEDEC Standard 100. To shorten the symbols, some of pin names and other related terminologies have been abbreviated as follows: Table 5-15. Timing Parameters SUBSCRIPTS SYMBOL PARAMETER c Cycle time (period) d Delay time dis Disable time en Enable time h Hold time su Setup time START Start bit t Transition time v Valid time w Pulse duration (width) X Unknown, changing, or don't care level F Fall time H High L Low R Rise time V Valid IV Invalid AE Active Edge FE First Edge LE Last Edge Z High impedance 5.9.2 Interface Clock Specifications 5.9.2.1 Interface Clock Terminology The interface clock is used at the system level to sequence the data and/or to control transfers accordingly with the interface protocol. 5.9.2.2 Interface Clock Frequency The two interface clock characteristics are: • The maximum clock frequency • The maximum operating frequency The interface clock frequency documented in this document is the maximum clock frequency, which corresponds to the maximum frequency programmable on this output clock. This frequency defines the maximum limit supported by the Device IC and does not take into account any system consideration (PCB, peripherals). The system designer will have to consider these system considerations and the Device IC timing characteristics as well to define properly the maximum operating frequency that corresponds to the maximum frequency supported to transfer the data on this interface. |
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