AD9163BBCZ datasheet(33/124 Pages) AD

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AD9163

Data Sheet

Rev. 0 | Page 32 of 123

The calibration code of the termination can be read from

Bits[3:0] in Register 0x2AC (PHY 0, PHY 1, PHY 6, PHY 7)

and Register 0x2B3 (PHY 2, PHY 3, PHY 4, PHY 5). If needed,

the termination values can be adjusted or set using several

registers. The TERM_BLKx_CTRLREG1 registers (Register 0x2A8

and Register 0x2AF), can override the autocalibrated value. When

set to 0xXXX0XXXX, the termination block autocalibrates,

which is the normal, default setting. When set to 0xXXX1XXXX,

the autocalibration value is overwritten with the value in Bits[3:1]

of Register 0x2A8 and Register 0x2AF. Individual offsets from the

autocalibration value for each lane can be programmed in Bits[3:0]

of Register 0x2BB to Register 0x2C2. The value is a signed magni-

tude, with Bit 3 as the sign bit. The total range of the termination

resistor value is about 94 Ω to 120 Ω, with approximately 3.5%

increments across the range (for example, smaller steps at the

bottom of the range than at the top).

Receiver Eye Mask

The AD9163 complies with the JESD204B specification

regarding the receiver eye mask and is capable of capturing data

that complies with this mask. Figure 92 shows the receiver eye

mask normalized to the data rate interval with a 600 mV VTT

swing. See the JESD204B specification for more information

regarding the eye mask and permitted receiver eye opening.

525

–55

–525

0.5

1.00

0.35

0.65

TIME (UI)

LV-OIF-11G-SR RECEIVER EYE MASK

Figure 92. Receiver Eye Mask for 600 mV VTT Swing

Clock Relationships

The following clocks rates are used throughout the rest of the

JESD204B section. The relationship between any of the clocks

can be derived from the following equations:

DataRate = (DACRate)/(InterpolationFactor)

LaneRate = (20 × DataRate × M)/L

ByteRate = LaneRate/10

This relationship comes from 8-bit/10-bit encoding, where each

byte is represented by 10 bits.

PCLK Rate = ByteRate/4

The processing clock is used for a quad-byte decoder.

FrameRate = ByteRate/F

where F is defined as octets per frame per lane.

PCLK Factor = FrameRate/PCLK Rate = 4/F

where:

M is the JESD204B parameter for converters per link.

L is the JESD204B parameter for lanes per link.

F is the JESD204B parameter for octets per frame per lane.

SERDES PLL

Functional Overview of the SERDES PLL

The independent SERDES PLL uses integer N techniques to

achieve clock synthesis. The entire SERDES PLL is integrated

on chip, including the VCO and the loop filter. The SERDES

PLL VCO operates over the range of 6 GHz to 12.5 GHz.

In the SERDES PLL, a VCO divider block divides the VCO

clock by 2 to generate a 3 GHz to 6.25 GHz quadrature clock for

the deserializer cores. This clock is the input to the clock and

data recovery block that is described in the Clock and Data

Recovery section.

The reference clock to the SERDES PLL is always running at a

frequency, fREF, that is equal to 1/40 of the lane rate (PCLK Rate).

This clock is divided by a DivFactor value (set by SERDES_PLL_

DIV_FACTOR) to deliver a clock to the phase frequency detector

(PFD) block that is between 35 MHz and 80 MHz. Table 17

includes the respective SERDES_PLL_DIV_FACTOR register

settings for each of the desired PLL_REF_CLK_RATE options

available.

Table 17. SERDES PLL Divider Settings

Lane Rate

(Gbps)

PLL_REF_CLK_RATE,

SERDES_PLL_DIV_FACTOR

0.750 to 1.5625

0b01 = 2×

0b10 = ÷1

1.5 to 3.125

0b00 = 1×

0b10 = ÷1

3 to 6.25

0b00 = 1×

0b01 = ÷2

6 to 12.5

0b00 = 1×

0b00 = ÷4

To enable the SERDES PLL, first set the PLL divider register (see

Table 17). Then enable the SERDES PLL by writing Register 0x280,

Bit 0 = 1. If a recalibration is needed, write Register 0x280, Bit 2 =

0b1 and then reset the bit to 0b0. The rising edge of the bit causes a

recalibration to begin.

Confirm that the SERDES PLL is working by reading

has locked. If Register 0x281, Bit 3 = 1, the SERDES PLL was

successfully calibrated. If Register 0x281, Bit 4 or Bit 5 is high, the

PLL reaches the lower or upper end of its calibration band and

must be recalibrated by writing 0 and then 1 to Register 0x280,

Bit 2.

AD9163BBCZ Datasheet(PDF) 33 Page - Analog Devices

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