AD9163BBCZ datasheet(6/124 Pages) AD

6 / 124 page

Data Sheet

AD9163

Rev. 0 | Page 5 of 123

Parameter

Test Conditions/Comments

Min

Typ

Max

Unit

POWER DISSIPATION

3 GSPS

2× NRZ Mode, 6×, FIR85 Enabled, NCO On

Using 80%, 3× filter, eight-lane JESD204B

2.1

NRZ Mode, 24×, FIR85 Disabled, NCO On

Using 80%, 2× filter, one-lane JESD204B

1.3

5 GSPS

NRZ Mode, 8×, FIR85 Disabled, NCO On

Using 80%, 2× filter, eight-lane JESD204B

2.18

NRZ Mode, 16×, FIR85 Disabled, NCO On

Using 80%, 2× filter, eight-lane JESD204B

2.09

2× NRZ Mode, 6×, FIR85 Enabled, NCO On

Using 80%, 3× filter, eight-lane JESD204B

2.65

SERIAL PORT AND CMOS PIN SPECIFICATIONS

VDD25_DAC = 2.5 V, VDD12A = VDD12_CLK = 1.2 V, VNEG_N1P2 = −1.2 V, DVDD = 1.2 V, IOVDD = 2.5 V, VDD_1P2 =

DVDD_1P2 = PLL_LDO_VDD12 = 1.2 V, SYNC_VDD_3P3 = 3.3 V, IOUTFS = 40 mA, TA = −40°C to +85°C, unless otherwise noted.

Table 4.

Parameter

Symbol

Test Comments/Conditions

Min

Typ

Max

Unit

WRITE OPERATION

See Figure 89

Maximum SCLK Clock Rate

fSCLK, 1/tSCLK

100

MHz

SCLK Clock High

tPWH

SCLK = 20 MHz

3.5

SCLK Clock Low

tPWL

SCLK = 20 MHz

SDIO to SCLK Setup Time

tDS

SCLK to SDIO Hold Time

tDH

0.5

CS to SCLK Setup Time

SCLK to CS Hold Time

0.5

READ OPERATION

See Figure 88

SCLK Clock Rate

fSCLK, 1/tSCLK

MHz

SCLK Clock High

tPWH

SCLK Clock Low

tPWL

SDIO to SCLK Setup Time

tDS

SCLK to SDIO Hold Time

tDH

CS to SCLK Setup Time

SCLK to SDIO (or SDO) Data Valid Time

tDV

CS to SDIO (or SDO) Output Valid to High-Z

Not shown in Figure 88 or

Figure 89

INPUTS (SDIO, SCLK, CS, RESET, TX_ENABLE)

Voltage Input

High

VIH

1.8 V ≤ IOVDD ≤ 2.5 V

0.7 × IOVDD

Low

VIL

1.8 V ≤ IOVDD ≤ 2.5 V

0.3 × IOVDD

Current Input

High

IIH

µA

Low

IIL

−150

µA

OUTPUTS (SDIO, SDO)

Voltage Output

High

VOH

1.8 V ≤ IOVDD ≤ 3.3 V

0.8 × IOVDD

Low

VOL

1.8 V ≤ IOVDD ≤ 3.3 V

0.2 × IOVDD

Current Output

High

IOH

Low

IOL

AD9163BBCZ Datasheet(PDF) 6 Page - Analog Devices

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