AD9163BBCZ datasheet(64/124 Pages) AD

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Data Sheet

AD9163

Rev. 0 | Page 63 of 123

VCO

PLL

ADF4355

fREF

2GHz TO 6GHz

0dBm

100pF

7.4nH

VOUT

7.4nH

100pF

AD9163

CLK+

CLK–

OUTPUT

STAGE

Figure 134. Possible Signal Chain for CLK± Input

ANALOG OUTPUTS

Equivalent DAC Output and Transfer Function

The AD9163 provides complementary current outputs, OUTPUT+

and OUTPUT−, that sink current from an external load that is

referenced to the 2.5 V VDD25_DAC supply. Figure 135 shows

an equivalent output circuit for the DAC. Compared to most

current output DACs of this type, the outputs of the AD9163

consists of a constant current (IFIXED), and a peak differential ac

current, ICS (ICS = ICSP + ICSN). These two currents combine to

form the IINTx currents shown in Figure 135. The internal

currents, IINTP and IINTN, are sent to the output pin and to an

input termination resistance equivalent to 100 Ω pulled to the

VDD25_DAC supply (RINT). This termination serves to divide the

output current based on the external termination resistors that

are pulled to VDD25_DAC.

ICSP

IOUTFS = 8mA TO 40mA

VDD25_DAC

100Ω

OUTPUT+

OUTPUT–

100Ω

ICSN

IFIXED

IINTN

IINTP

Figure 135. Equivalent DAC Output Circuit

The example shown in Figure 135 can be modeled as a pair of

dc current sources that source a current of IOUTFS to each output.

This differential ac current source is used to model the signal

(that is, a digital code) dependent nature of the DAC output.

The polarity and signal dependency of this ac current source are

related to the digital code (F) by the following equation:

F (code) = (DACCODE – 32,768)/32,768

(2)

where:

−1 ≤ F (code) < +1.

DACCODE = 0 to 65,535 (decimal).

The current that is measured at the OUTPUT+ and OUTPUT−

outputs is as follows:

OUTPUT+ = (IFIXED (mA) + (F × IOUTFS)/FMAX(mA)) ×

(RINT/(RINT + RLOAD)

(3)

OUTPUT− = (IFIXED (mA) + ((FMAX − F) × IOUTFS)/FMAX(mA)) ×

(RINT/(RINT + RLOAD)

The IFIXED value is about 3.8 mA. It is important to note that the

AD9163 output cannot support dc coupling to the external load,

and thus must be ac-coupled through appropriately sized capacitors

for the chosen operating frequencies. Figure 136 shows the

OUTPUT+ vs. DAC code transfer function when IOUTFS is set to

40 mA.

DAC CODE

16384

32768

49152

65536

Figure 136. Gain Curve for ANA_FULL_SCALE_CURRENT[9:0] = 1023, DAC

Offset = 3.8 mA

Peak DAC Output Power Capability

The maximum peak power capability of a differential current

output DAC is dependent on its peak differential ac current,

IPEAK, and the equivalent load resistance it sees. In the case of a

1:1 balun with 100 Ω differential source termination, the equiva-

lent load that is seen by the DAC ac current source is 50 Ω. If

the AD9163 is programmed for an IOUTFS = 40 mA, its ideal peak

ac current is 20 mA and its maximum power, delivered to the

equivalent load, is 10 × (RINT/(RINT + RLOAD) = 8 mW (that is, P =

I2R). Because the source and load resistance seen by the 1:1

balun are equal, this power is shared equally. Therefore, the

output load receives 4 mW, or 6 dBm maximum power.

To calculate the rms power delivered to the load, consider the

following:

•

Peak to rms ratio of the digital waveform

•

Any digital backoff from digital full scale

•

DAC sinc response and nonideal losses in the external

network

•

DAC analog roll-off due to switch parasitic capacitance and

load impedance

AD9163BBCZ Datasheet(PDF) 64 Page - Analog Devices

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