AD9371BBCZ datasheet(57/60 Pages) AD

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Data Sheet

AD9371

Rev. A | Page 57 of 60

THEORY OF OPERATION

The AD9371 is a highly integrated RF transceiver that can be

configured for a wide range of applications. The device integrates

all the RF, mixed-signal, and digital blocks necessary to provide

transmit and receive functions in a single device. Programmability

allows the two receiver channels and two transmitter channels

to be used in TDD and FDD systems for 3G and 4G cellular

standards.

The observation receiver channel has two inputs for use in

monitoring the transmitter outputs. This channel has a wide

channel bandwidth that receives the entire transmit band and

feeds it back to the digital section for error correction purposes.

In addition, three sniffer receiver inputs can monitor different

radio frequency bands (one at a time). These channels share the

baseband ADC and digital processing with the two ORx inputs.

The AD9371 contains four high speed serial interface links for

the transmit chain and four high speed serial interface links

shared by the Rx, ORx, and SnRx channels (JESD204B,

Subclass 1 compliant), providing a low pin count and reliable

data interface to a field-programmable gate array (FPGA) or

other custom integrated baseband solutions.

The AD9371 also provides self calibration for dc offset, LO

leakage, and quadrature error correction using an integrated

microcontroller core to maintain a high performance level

under varying temperatures and input signal conditions. Firmware

is supplied with the device to schedule all calibrations with no

user interaction. The device includes test modes that allows

system designers to debug designs during prototyping and

optimize radio configurations.

TRANSMITTER (Tx)

The AD9371 employs a direct conversion transmitter

architecture consisting of two identical and independently

controlled channels that provide all the digital processing,

mixed signal, and RF blocks necessary to implement a direct

conversion system. Both channels share a common frequency

synthesizer.

The digital data from the JESD204B lanes pass through a fully

programmable 96-tap FIR filter with optional interpolation.

The FIR output is sent to a series of conversion filters that

provide additional filtering and data rate interpolation prior to

reaching the DAC. Each DAC has an adjustable sample rate and

is linear up to full scale.

When converted to baseband analog signals, the in-phase (I) and

quadrature (Q) signals are filtered to remove sampling artifacts,

and then the signals are fed to the upconversion mixers. At the

mixer stage, the I and Q signals are recombined and modulated

onto the carrier frequency for transmission to the output stage.

Each transmit chain provides a wide attenuation adjustment

range with fine granularity to help designers optimize SNR.

RECEIVER (Rx)

The AD9371 contains dual receiver channels. Each Rx channel

is a direct conversion system that contains a programmable

attenuator stage, followed by matched I and Q mixers that

downconvert received signals to baseband for digitization.

To achieve gain control, a programmed gain index map is

implemented. This gain map distributes attenuation among the

various Rx blocks for optimal performance at each power level.

In addition, support is available for both automatic and manual

gain control modes.

The receiver includes Σ-Δ ADCs and adjustable sample rates

that produce data streams from the received signals. The signals

can be conditioned further by a series of decimation filters and

a fully programmable 72-tap FIR filter with additional decimation

settings. The sample rate of each digital filter block is adjustable

by changing the decimation factors to produce the desired

output data rate.

OBSERVATION RECEIVER (ORx)

The ORx operates in a similar manner to the main receivers.

Each input is differential and uses a dedicated mixer. The ORx

inputs share a baseband ADC and baseband section; therefore,

only one can be active at any time. The mixed-signal and digital

section is identical in design and operation to the main receiver

channels. This channel can monitor the Tx channels and

implement error correction functions. It can also be used as a

general-purpose receiver.

SNIFFER RECEIVER (SnRx)

The sniffer receiver provides three differential inputs that can

monitor different frequency bands. Each input has a low noise

amplifier (LNA) that is multiplexed to feed a single mixer. The

output of this mixer stage is multiplexed with the ORx receiver

mixers to feed the same baseband section. The SnRx bandwidth

is limited to 20 MHz. This receiver can also be used as a general-

purpose receiver if the bandwidth and RF performance are

acceptable for a given application.

These receiver inputs also provide an LNA bypass mode that

removes the gain of the LNA when large signals are present.

Note that no requirements for the LNA bypass mode are included

in Table 1; performance specifications are only relative to the

scenario in which the LNA is enabled.

CLOCK INPUT

The AD9371 requires a differential clock connected to the

DEV_CLK_IN+/DEV_CLK_IN− pins. The frequency of the

clock input must be between 10 MHz and 320 MHz, and it must

have very low phase noise because this signal generates the RF

local oscillator and internal sampling clocks.

AD9371BBCZ Datasheet(PDF) 57 Page - Analog Devices

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