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AD9371BBCZ Datasheet(PDF) 11 Page - Analog Devices |
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AD9371BBCZ Datasheet(HTML) 11 Page - Analog Devices |
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11 / 60 page  Data Sheet AD9371 Rev. A | Page 11 of 60 TIMING SPECIFICATIONS Table 3. Parameter Symbol Min Typ Max Unit Test Conditions/Comments SERIAL PERIPHERAL INTERFACE (SPI) TIMING SCLK Period tCP 20 ns SCLK Pulse Width tMP 10 ns CSB Setup to First SCLK Rising Edge tSC 3 ns Last SCLK Falling Edge to CSB Hold tHC 0 ns SDIO Data Input Setup to SCLK tS 2 ns SDIO Data Input Hold to SCLK tH 0 ns SCLK Falling Edge to Output Data Delay (3- or 4-Wire Mode) tCO 3 8 ns Bus Turnaround Time After Baseband Processor (BBP) Drives Last Address Bit tHZM tH tCO ns Bus Turnaround Time After AD9371 Drives Last Address Bit tHZS 0 tCO ns DIGITAL TIMING TXx_ENABLE Pulse Width 10 µs RXx_ENABLE Pulse Width 10 µs JESD204B DATA OUTPUT TIMING Unit Interval UI 162.76 1627.6 ps Data Rate per Channel (Nonreturn to Zero (NRZ)) 614.4 6144 Mbps Rise Time tR 24 35 ps 20% to 80% in 100 Ω load Fall Time tF 24 35 ps 20% to 80% in 100 Ω load Output Common-Mode Voltage VCM 0 1.8 V AC-coupled Termination Voltage (VTT) = 1.2 V 735 1135 mV DC-coupled Differential Output Voltage VDIFF 360 466 770 mV Short-Circuit Current IDSHORT −100 +100 mA Differential Termination Impedance ZRDIFF 80 100 120 Ω Total Jitter 17 48.8 ps Bit error rate (BER) = 10−15 Uncorrelated Bounded High Probability Jitter UBHPJ 1.2 24.4 ps Duty-Cycle Distortion DCD 3 8.1 ps SYSREF_IN Signal Setup Time to DEV_CLK_IN Signal tS 2.5 ns See Figure 2 and Figure 3 SYSREF_IN Signal Hold Time to DEV_CLK_IN Signal tH −1.5 ns See Figure 2 and Figure 3 JESD204B DATA INPUT TIMING Unit Interval UI 162.76 1627.6 ps Data Rate per Channel (NRZ) 614.4 6144 Mbps Input Common-Mode Voltage VCM 0.05 1.85 V AC-coupled VTT = 1.2 V 720 1200 mV DC-coupled Differential Input Voltage VDIFF 125 750 mV VTT Source Impedance ZTT 1.2 30 Ω Differential Termination Impedance ZRDIFF 80 106 120 Ω VTT AC-Coupled 1.27 1.33 V DC-Coupled 1.14 1.26 V |
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