PC87351 datasheet(25/86 Pages) NSC

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2.0 Device Architecture and Configuration (Continued)

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2.2

CONFIGURATION STRUCTURE AND ACCESS

This section describes the structure of the configuration register file, and the method of accessing the configuration registers.

2.2.1

The Index-Data Register Pair

The SuperI/O configuration access is performed via an Index-Data register pair, using only two system I/O byte locations.

The base address of this register pair is determined during reset, according to the state of the hardware strapping option on

the BADDR pin. Table 2-1 shows the selected base addresses as a function of BADDR.

Table 2-1. BADDR Strapping Options

The Index Register is an 8-bit R/W register located at the selected base address (Base+0). It is used as a pointer to the

configuration register file, and holds the index of the configuration register that is currently accessible via the Data Register.

Reading the Index Register returns the last value written to it (or the default of 00h after reset).

The Data Register is an 8-bit virtual register, used as a data path to any configuration register. Accessing the data register

results with physically accessing the configuration register that is currently pointed by the index register.

2.2.2

Banked Logical Device Registers

Each functional block is associated with a Logical Device Number (LDN). The configuration registers are grouped into banks,

where each bank holds the standard PnP configuration registers of the corresponding logical device. Table 2-2 shows the

LDNs of the device functional blocks.

Figure 2-2 shows the structure of the standard PnP configuration register file. The SIO Control and Configuration registers

are not banked and are accessed by the Index-Data register pair only, as described above. However, the device control and

device configuration registers are duplicated over 9 banks for 9 logical devices. Therefore, accessing a specific register in

a specific bank is performed by two dimensional indexing, where the LDN Register selects the bank (or logical device) and

the Index Register selects the register within the bank. Accessing the Data Register while the Index Register holds a value

of 30h or higher results in a physical access to the configuration register currently pointed to by the Index Register, within

the logical device currently selected by the LDN Register.

Figure 2-2. Structure of the PnP Standard Registers

BADDR

I/O Address

Index Register

Data Register

002Eh

002Fh

015Ch

015Dh

07h

20h

30h

60h

75h

F2h

Logical Device Number Register

SuperI/O Configuration Registers

Logical Device Control Register

Logical Device Configuration

Special (Vendor-defined) Registers

9 Banks - One per

Logical Device

2Eh

F0h

Bank Select

63h

74h

70h

71h

PnP Standard Registers

PC87351 Datasheet(PDF) 25 Page - National Semiconductor (TI)

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