PC87351 datasheet(30/86 Pages) NSC

30 / 86 page

2.0 Device Architecture and Configuration (Continued)

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2.3

The register maps in this chapter use the following abbreviations for Type:

• R/W = Read/Write

• R = Read from a speciﬁc address returns the value of a speciﬁc register. Write to the same address is to a different

• W = Write

• RO = Read Only

• R/W1C = Read/Write 1 to Clear. Writing 1 to a bit clears it to 0. Writing 0 has no effect.

2.4

SUPERI/O CONFIGURATION AND CONTROL REGISTERS

This section describes the registers with first level indexes in the range 07h - 2Fh.

2.4.1

SuperI/O Register Map

2.4.2

SuperI/O ID Register (SID)

This register contains the identity number of the chip. The PC87351 is identified by the value E2h.

Location:

Index 20h

Type:

Index Mnemonic

Name

Type

Section

07h

LDN

Logical Device Number Register

R/W

2.2.2

20h

SID

SuperI/O ID Register

2.4.2

21h

SIOCF1

SuperI/O Conﬁguration 1 Register

R/W

2.4.3

22h

SIOCF2

SuperI/O Conﬁguration 2 Register

R/W

23h

SIOCF3

SuperI/O Conﬁguration 3 Register

R/W

2.4.5

24h

SIOCF4

SuperI/O Conﬁguration 4 Register

R/W

2.4.6

27h

SRID

SuperI/O Revision ID Register

2.4.7

2Eh

Reserved exclusively for National use

Bit

76543210

Name

Chip ID

Reset

11100010

PC87351 Datasheet(PDF) 30 Page - National Semiconductor (TI)

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