PC87351 datasheet(65/86 Pages) NSC

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5.0 Fan Speed Control (Continued)

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5.3

FAN SPEED CONTROL REGISTERS

The register maps in this chapter use the following abbreviations for Type:

• R/W = Read/Write

• R = Read from a speciﬁc address returns the value of a speciﬁc register. Write to the same address is to a different

• W = Write

• RO = Read Only

• R/W1C = Read/Write 1 to Clear. Writing 1 to a bit clears it to 0. Writing 0 has no effect.

5.3.1

Fan Speed Control Register Map

5.3.2

Fan Control Pre-Scale Register (FCPSR)

Location:

Device specific

Type:

R/W

5.3.3

Fan Control Duty Cycle Register (FCDCR)

Location:

Device specific

Type:

R/W

1. The location of this register is deﬁned in the

Device Architecture and Conﬁguration chapter in

Section 2.13.1.

Offset

Mnemonic

Name

Type

Section

Device specific1

FCPSR

Fan Speed Control Pre-Scale Register

R/W

5.3.2

Device specific1

FCDCR

Fan Speed Control Duty Cycle Register

R/W

5.3.3

Bit

76543210

Name

Clock

Select

Pre-Scale Value

Reset

00000000

Bit

Description

Clock Select. This bit selects the input clock for the clock divider.

0: 24 MHz

1: 200 KHz

6-0

Pre-Scale Value. The clock divider for the input clock (24 MHz or 200 KHz) is Pre-Scale Value + 1. Writing 0

transfers the input clock directly to the counter. The maximum clock divider is 124 (7Bh +1). These bits must not

be programmed with the values 7Ch, 7Dh, 7Eh and 7Fh as this may produce unpredictable results.

The contents of this register should not be changed when the corresponding Fan Speed Control Enable bit of

the Fan Speed Control Conﬁguration Register is 1 (See

Device Architecture and Conﬁguration chapter).

Otherwise, there may be unpredictable results.

Bit

76543210

Name

Duty Cycle Value

Reset

11111111

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