PC87351 datasheet(28/86 Pages) NSC

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2.0 Device Architecture and Configuration (Continued)

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2.2.4

Overview of PnP Standard Registers

Figure 2-3. PnP Register Map

SuperI/O Control and Conﬁguration Registers

The only implemented PnP control register in the PC87351 is the Logical Device Number Register at index 07h. All the other

standard PnP control registers are associated with PnP protocol for ISA add-in cards, and are not supported by the PC87351.

The SuperI/O Configuration registers at indexes 20h and 27h are mainly used for part identification, global power manage-

ment and the selection of pin multiplexing options. For details, see Section 2.5.

Logical Device Control and Conﬁguration Registers

A subset of these registers is implemented for each logical device.

Control

The only implemented logical device control register is the activate register at index 30. Bit 0 of the activate register controls

the activation of the associated function block. Activation of the block enables access to the block’s registers, and attaches

its system resources, which are unused as long as the block is not activated. Other effects may apply, on a function-specific

basis (such as clock enable and active pinout signaling).

Standard Conﬁguration

The standard configuration registers are used to manage the PnP resource allocation to the functional blocks. The I/O port

base address descriptor 0 is a pair of registers at Index 60-61, holding the (first or only) 16-bit base address for the register

set of the functional block. An optional second base-address (descriptor 1) at index 62-63 is used for devices with more than

one continuous register set. IRQ Number Select (index 70h) and IRQ Type Select (index 71h) allocate an IRQ line to the

block and control its type. DMA Channel Select 0 (index 74h) allocates a DMA channel to the block, where applicable. DMA

Channel Select 1 (index 75h) allocates a second DMA channel, where applicable.

SuperI/O Control and

Conﬁguration Registers

Logical Device Control and

one per logical device

Conﬁguration Registers -

Index

Name

07h

Logical Device Number Register

20h

SuperI/O ID Register

21h

SuperI/O Conﬁguration 1 Register

22h

SuperI/O Conﬁguration 2 Register

23h

SuperI/O Conﬁguration 3 Register

24h

SuperI/O Conﬁguration 4 Register

27h

SuperI/O Revision ID Register

2Eh

Reserved exclusively for National use

30h

Logical Device Control Register (Activate)

60h

I/O Base Address Descriptor 0 Bits 15-8

61h

I/O Base Address Descriptor 0 Bits 7-0

62h

I/O Base Address Descriptor 1 Bits 15-8

63h

I/O Base Address Descriptor 1 Bits 7-0

70h

IRQ Number Select

71h

IRQ Type Select

74h

DMA Channel Select 0

75h

DMA Channel Select 1

F0h

Device Speciﬁc Logical Device Conﬁguration 1

F1h

Device Speciﬁc Logical Device Conﬁguration 2

F2h

Device Speciﬁc Logical Device Conﬁguration 3

(some are optional)

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