PC87351 datasheet(64/86 Pages) NSC

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5.0 Fan Speed Control

5.1

OVERVIEW

This chapter describes one Fan Speed Control module. A device may include some modules with different implementations.

For the device specific implementation, see the

Device Architecture and Configuration chapter.

The Fan Speed Control is a programmable Pulse Width Modulation (PWM) generator. The PWM output is used to control

the fan’s power voltage, which is correlated to the fan’s speed. Converting a 0 to 100% duty cycle PWM signal to an analog

voltage range is achieved by an external circuit, as shown in Figure 5-1. Some new types of fans accept direct PWM input

without any external circuitry.

Figure 5-1. Fan Speed Control - System Conﬁguration

5.2

FUNCTIONAL DESCRIPTION

The PWM generator operation is based on a PWM counter and two registers: the Fan Speed Control Pre-Scale Register

(FCPSR), used to determine the overall cycle time (or the frequency) of the FANOUT output, and the Fan Speed Control

Duty Cycle Register (FCDCR), used to determine the duty cycle of the FANOUT between 0 to 100%.

The PWM counter is an 8-bit, free-running counter that runs continuously in a cyclic manner, i.e its cycle equals 256 clock

periods. The PWM output is high as long as the count is lower than the FCDCR value, and flips to low as the counter exceeds

that value. The duty cycle (expressed as a percentage) is therefore (FCDCR/256)*100. In particular, the PWM output is con-

tinuously low when FCDCR=0 and continuously high when FCDCR=FFh. The FANOUT output may be inverted by an ex-

ternal configuration bit, in which case the FANOUT duty cycle is ([256-FCDCR]/256)*100.

The PWM counter clock is generated by dividing the input clock, either 24 MHz or 200 KHz (according to Clock Select, bit

7 of the FCPSR Register) using a clock divider. The division factor, which must be between 1 and 124, is defined as Pre-

Scale Value+1, where Pre-Scale is the binary value stored in bits 6 to 0 of the FCPSR Register. The resulting PWM output

frequency is therefore (24 MHz or 200 kHz/([Pre-Scale Value+1]*256). The default selection of 24 MHz input clock allows a

programmable FANOUT frequency in the range of 756 Hz to 93.75 KHz. For lower frequencies, selecting the 200 KHz input

clock allows a frequency range of 6 Hz to 781 Hz. See Figure 5-2.

The FANOUT frequency must be pre-selected according to the fan type specific requirements prior to enabling the Fan

Speed Control. The only run-time change that is required to dynamically control the fan speed is the value of the FCDCR

Fan Speed

Control

Fan

FANOUT

Control

External

Circuitry

External

Circuitry

24 MHz

(1-124)

PWM

FCDCR Register

FCDCR > Counter

FANOUT

FCPSR Register

Figure 5-2. PWM Generator (FANOUT)

Invert

200 KHz

Bit 7

Bits 6-0

PWM Output -

Counter

Comparator

FANOUT

Clock

Divider

PC87351 Datasheet(PDF) 64 Page - National Semiconductor (TI)

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