PC87351 datasheet(34/86 Pages) NSC

34 / 86 page

2.0 Device Architecture and Configuration (Continued)

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2.4.6

SuperI/O Configuration 4 Register (SIOCF4)

This register controls the multiplexing of two pins. Its value is retained by VPP, and is not affected by either hardware or soft-

ware reset.

Location:

Index 24h

Type:

R/W

2.4.7

SuperI/O Revision ID Register (SRID)

This read only register contains the identity number of the chip revision. SRID is incremented on each revision.

Location:

Index 27h

Type:

Bit

76543210

Name

SUSP Value

General Purpose Scratch

PME2

Debounce

Enable

Pin 126

Function

Select

PME1

Debounce

Enable

Pin 125

Function

Select

Reset

0001010

Bit

Description

SUSP Value. Last value of SUSP pin prior to VSB loss (power-fail).

6-4

General Purpose Scratch. Battery-backed.

PME2 Debounce Enable

0: Debounce disabled

1: 16mS debounce enabled (VPP power-up default)

Pin 126 Function Select

0: Pin 126 functions as SUSP (VPP power-up default)

1: Pin 126 functions as PME2

PME1 Debounce Enable

0: Debounce disabled

1: 16mS debounce enabled (VPP power-up default)

Pin 125 Function Select

0: RING (VPP power-up default)

1: PME1

PC87351 Datasheet(PDF) 34 Page - National Semiconductor (TI)

PC87351 Datasheet(HTML) 34 Page - National Semiconductor (TI)

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