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4.0 General-Purpose Input/Output (GPIO) Port

This chapter describes one 8-bit port. A device may include a combination of several ports with different implementations.

For the device specific implementation, see the

Device Architecture and Configuration chapter. If there are fewer than 8 bits

per port in a configuration, only the corresponding lower bits are implemented and the remaining bits are reserved. For in-

stance, if there are 3 bits per port, only bits 0-2 are implemented, and the remaining 5 bits are reserved.

4.1

OVERVIEW

The GPIO port is an 8-bit port which is based on eight pins. It features:

• Software capability to manipulate and read pin levels

• Controllable interrupt assertion based on the pin level or level transition

• Ability to capture and manipulate interrupts and their associated status

• Back-drive protected pins.

GPIO port operation is associated with two sets of registers:

• Conﬁguration registers, mapped in the Device Conﬁguration space. These registers are used to statically set up the

logical behavior of each pin. There is one 8-bit register for each GPIO pin.

• Four 8-bit runtime registers: GPIO Data Out (GPDO), GPIO Data In (GPDI), GPIO Interrupt Enable (GPIEN) and

GPIO Status (GPST). These registers are mapped in the GPIO device IO space (which is determined by the base

address registers in the GPIO Device Conﬁguration). They are used to manipulate and/or read the pin values, and to

control and handle interrupt generation. Each runtime register corresponds to the 8-pin port, such that bit n in each

one of the four registers is associated with GPIOXn pin, where X is the port number.

Each GPIO pin is associated with eight configuration bits and the corresponding bit slice of the four runtime registers, as

shown in Figure 4-1.

The functionality of the GPIO port is divided into basic functionality that includes the manipulation and reading of the GPIO

pins. This functionality is described in Section 4.2. The enhanced functionality which includes the interrupt assertion and

handling is described in Section 4.3.

Figure 4-1. GPIO Port Architecture

Pin Conﬁguration

Select Register

Access Register

GPDOX

GPDIX

GPIENX

GPSTX

Runtime

Registers

GPIOX Base Address

Interrupt Pending

Bit n

Pin Select

8 GPIO Conﬁguration

Registers

GPIOXn

GPIOXn CNFG

Interrupt Request

GPIOXn

Port Logic

X = port number;

n = 0 to 7

PC87351 Datasheet(PDF) 57 Page - National Semiconductor (TI)

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