PC87351 datasheet(60/86 Pages) NSC

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4.0 General-Purpose Input/Output (GPIO) Port (Continued)

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A GPIO pin is in interrupt pending state if the corresponding bit of the GPIEN Register is set and either:

• The IRQ Type is level and the pin is in active level, or

• The IRQ Type is edge and the corresponding bit of the GPST Register is set.

The target IRQ line is asserted if at least one GPIO pin is in interrupt pending state. The selection of the target IRQ line is

determined by the IRQ selection procedure of the device configuration. The assertion of the IRQ line is blocked when the

GPIO functional block is deactivated.

If the output is enabled, the IRQ may be initiated by the software when writing to the GPDO Register.

An edge interrupt may be de-asserted by clearing the corresponding GPST bit. However, a level Interrupt source may not

be released by software (except for disabling the source), as long as the pin is in active level. When level interrupt is used,

it is recommended to disable the input debouncer.

Upon de-activation of the GPIO port, the GPST Register is cleared and access to both the GPST and GPIEN Registers is

disabled. The target IRQ line is detached from the GPIO and de-asserted.

Before enabling the interrupts, it is recommended to set the desired interrupt configuration, and then verify that the status

registers are cleared.

4.4

GPIO PORT REGISTERS

The register maps in this chapter use the following abbreviations for Type:

• R/W = Read/Write

• R = Read from a speciﬁc address returns the value of a speciﬁc register. Write to the same address is to a different

• W = Write

• RO = Read Only

• R/W1C = Read/Write 1 to Clear. Writing 1 to a bit clears it to 0. Writing 0 has no effect.

4.4.1

GPIO Pin Configuration Access Register

This is a group of eight identical configuration registers, each of which is associated with one GPIO pin. The entire set is

mapped to the PnP configuration space. The mapping scheme is based on the GPIO Pin Configuration Select Register that

functions as an index register, and the specific GPIO Pin Configuration Access Register that reflects the configuration of the

currently selected pin. For details on the GPIO Pin Configuration Select Register, refer to the

Device Architecture and Con-

figuration chapter.

Bits 4-6 are applicable only for the enhanced GPIO port with interrupt support. In the basic port. these bits are reserved,

return 0 on read and have no effect on port functionality.

Location:

Device specific

Type:

R/W (bit 3 is set only)

Bit

76543210

Name

Reserved

IRQ

Debounce

Enable

IRQ Polarity IRQ Type

Lock

Pull-Up

Control

Output

Type

Output

Enable

Reset

01000100

Bit

Description

Reserved

IRQ Debounce Enable

0: Disabled

1: Enabled (default)

IRQ Polarity. This bit deﬁnes the polarity of the signal that issues an interrupt from the corresponding GPIO pin

(falling/low or rising/high).

0: Falling edge or low level input (default)

1: Rising edge or high level input

PC87351 Datasheet(PDF) 60 Page - National Semiconductor (TI)

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