PC87351 datasheet(31/86 Pages) NSC

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2.0 Device Architecture and Configuration (Continued)

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2.4.3

SuperI/O Configuration 1 Register (SIOCF1)

Location:

Index 21h

Type:

R/W

Bit

76543210

Name

General Purpose

Scratch

Lock

Scratch

PNF Status

Reserved

Function

Lock

SW Reset

Global

Device

Enable

Reset

00010001

Bit

Description

7-6

General Purpose Scratch. When bit 5 is set to 1, these bits are read only. After reset, these bits can be read

or write. Once changed to read only, the bits can be changed back to read/write only by a hardware reset.

Lock Scratch. This bit controls bits 7 and 6 of this register. Once this bit is set to 1 by software, it can be

cleared to 0 only by a hardware reset.

0: Bits 7 and 6 of this register are read/write bits (default).

1: Bits 7 and 6 of this register are read only bits.

PNF Status. This read only bit reﬂects the value of the PNF pin when PPM mode is enabled. If PPM mode is

disabled, this bit is 1. Data written to this bit is ignored.

Reserved

Pin Function Lock. When this bit is set to 1, all function selection on the associated pins is locked:

• All bits of the SIOCF2 Register

• Bits 4-0 of the SIOCF3 Register

• Bits 3-0 of the SIOCF4 Register.

When this bit is set to 1 by software, it can only be cleared to 0 by MR or power-off.

0: No effect (default)

1: Pin function locked

SW Reset. Read always returns 0.

0: Ignored (default)

1: Resets all the devices that are reset by MR (with the exception of the lock bits) and the registers of the SWC

Global Device Enable. This bit controls the function enable of all the logical devices in the PC87351, except the

SWC. It allows them to be disabled simultaneously by writing to a single bit.

0: All logical devices in the PC87351 disabled, except SWC

1: Each logical device enabled according to its Activate Register at index 30h (default)

PC87351 Datasheet(PDF) 31 Page - National Semiconductor (TI)

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