PC87351 datasheet(29/86 Pages) NSC

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2.0 Device Architecture and Configuration (Continued)

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Special Conﬁguration

The vendor-defined registers, starting at index F0h are used to control function-specific parameters such as operation

modes, power saving modes, pin TRI-STATE, clock rate selection, and non-standard extensions to generic functions.

2.2.5

Default Configuration Setup

The device has four reset types, described below. See specific register descriptions for bits affected by each register type.

• Software Reset

This reset is enabled by bit 1 of the SIOCF1 Register, which resets all logical devices. A software reset also resets most

bits in the SuperI/O Configuration and Control Registers.

• Hardware Reset

This reset is activated by the assertion of the MR input. It resets all logical devices, with the exception of the SWC. It

also resets all SuperI/O Configuration and Control Registers, with the exception of the SIOCF4 Register.

• V

PP Power-Up Reset

This reset is activated when either VSB or VBAT is powered on after both have been off. VPP is an internal voltage which

is a combination of VSB and VBAT. VPP is taken from VSB if VSB is greater than the minimum (Min) value defined in the

Device Characteristics chapter; otherwise, VBAT is used as the VPP source. This reset resets all registers whose values

are retained by VPP.

• V

SB Power-Up Reset

This is an internally generated reset that resets the SWC, excluding those SWC registers whose values are retained by VPP.

The PC87351 wakes up with the default setup, as follows:

• In the event of a hardware reset:

— The conﬁguration base address is 2Eh or 15Ch, according to the BADDR strap pin value, as shown in Table 2-1.

— The Keyboard Controller (KBC) is active and all other logical devices are disabled, with the exception of the SWC

which remains functional but whose registers cannot be accessed.

— All the multiplexed GPIO pins, except KBRST/GPIO17/P12/PNF and GA20/GPIO20, are conﬁgured as GPIO pins

and are in TRI-STATE (default direction is input). KBRST/GPIO17/P12/PNF is conﬁgured as KBRST and

GA20/GPIO20 is conﬁgured as GA20.

• In the event of either a hardware or a software reset:

— The legacy devices are assigned with their legacy system resource allocation.

— The National proprietary functions are not assigned with any default resources and the default values of their base

addresses are all 00h.

2.2.6

Address Decoding

A full 16-bit address decoding is applied when accessing the configuration I/O space as well as the registers of the functional

blocks. However, the number of configurable bits in the base address registers vary for each device.

The lower 1, 2, 3 or 4 address bits are decoded within the functional block to determine the offset of the accessed register,

within the device’s I/O range of 2, 4, 8 or 16 bytes, respectively. The rest of the bits are matched with the base address

register to decode the entire I/O range allocated to the device. Therefore the lower bits of the base address register are

forced to 0 (read-only), and the base address is forced to be 2, 4, 8 or 16 byte aligned, according to the size of the IO range.

The base address of the FDC, Serial Port 1, Serial Port 2 and KBC are limited to the I/O address range of 00h to 7FXh only

(bits 11-15 are forced to 0). The Parallel Port base address is limited to the I/O address range of 00h to 3F8h. The addresses

of the non-legacy devices are configurable within the full 16-bit address range (up to FFFXh).

In some special cases, other address bits are used for internal decoding (such as bit 2 in the KBC and bit 10 in the PP). The

KBC has two I/O descriptors with some implied dependency between them. For more details, please see the detailed de-

scription of the base address register for each specific logical device.

2.2.7

The Internal Clocks

The source of the device internal clocks is a 48 MHz clock signal, which is routed through the CLKIN pin. Wake-up on KBD,

Mouse and RING pulse train detection operates on internally generated clock.

PC87351 Datasheet(PDF) 29 Page - National Semiconductor (TI)

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