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WM8233 Datasheet(PDF) 62 Page - Cirrus Logic

Part # WM8233
Description  210MSPS 6-Channel AFE with Sensor
PDF  146 Pages
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Manufacturer  CIRRUS [Cirrus Logic]
Direct Link  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

WM8233 Datasheet(HTML) 62 Page - Cirrus Logic

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WM8233
62
Rev 4.7
REGISTER MAP
The following table describes the location of each control bit used to determine the operation of the WM8233. Not all registers are
used and any registers not listed should be set to zero.
REG
NAME
7
6
5
4
3
2
1
0
DEFAULT
R0 (0h)
Software Reset/Chip ID 1
SW_RESET_CHIP_ID[7:0]
33h
R1 (1h)
Chip ID 2
CHIP_ID[7:0]
82h
R2 (2h)
Chip Rev
0
0
0
0
CHIP_REV[3:0]
00h
R3 (3h)
Setup Reg 1
0
0
0
ADC3PD
ADC2PD
ADC1PD
PDMD
PD
00h
R4 (4h)
Setup Reg 2
VVRLC_TOP_SEL PGAFS
ADCFS
0
0
0
CLPMD
CDS
00h
R5 (5h)
Setup Reg 3
0
0
0
SF_BYPLS
PT_SF[1:0]
SF_INP
SF_VRLC
1Ch
R6 (6h)
VRLC control
VRLCEN
VRLC_ISEL[1:0]
VRLC_VSEL[4:0]
8Ah
R7 (7h)
Output control
OE_OP
OUTPD
CMOSMODE
OUTSYNC
LVDSORDER
LVDSMODE[2:0]
40h
R8 (8h)
LVDS control
0
LVDS_POL
LVDS_AMP[2:0]
LVDS_VCM[2:0]
35h
R9 (9h)
LVDS clock pattern
0
LVCKPAT[6:0]
63h
R10 (Ah) Flag control 1
FLAG_S1[3:0]
FLAG_S0[3:0]
10h
R11 (Bh) Flag control 2
FLAG_S3[3:0]
FLAG_S2[3:0]
00h
R12 (Ch) Flag control 3
0
0
0
0
FLAG_S4[3:0]
00h
R13 (Dh) CMOS drivability control 1
0
0
0
0
DRV_CTRL
OP_DRV[2:0]
00h
R14 (Eh) CMOS drivability control 2
0
OP1_DRV[2:0]
0
OP0_DRV[2:0]
00h
R15 (Fh)
CMOS drivability control 3
0
OP3_DRV[2:0]
0
OP2_DRV[2:0]
00h
R16 (10h) CMOS drivability control 4
0
OP5_DRV[2:0]
0
OP4_DRV[2:0]
00h
R17 (11h) CMOS drivability control 5
0
OP7_DRV[2:0]
0
OP6_DRV[2:0]
00h
R18 (12h) CMOS drivability control 6
0
OP9_DRV[2:0]
0
OP8_DRV[2:0]
00h
R19 (13h) CMOS drivability control 7
0
OC2_DRV[2:0]
0
OC1_DRV[2:0]
00h
R20 (14h) PG config
PGMARCH
PGPAT[1:0]
PGINV
SEL_PGZ
SEL_PGY
SEL_PGX
PGEN
00h
R21 (15h) PGCODE LSB
PGLEVEL[7:0]
00h
R22 (16h) PGCODE MSB
PGLEVEL[15:8]
00h
R23 (17h) PG width 1
PGWIDTH1[7:0]
00h
R24 (18h) PG width 2
PGWIDTH2[7:0]
00h
R25 (19h) Clock monitor
0
0
0
0
0
MONCLK[2:0]
00h
R26 (1Ah) PLL control 1
0
0
0
0
0
PLL_LPF_RST PLL_CP_PD PLL_VCO_PD
00h
R27 (1Bh) PLL control 2
0
PLL_LPF_SEL
0
0
PLL_PFD_CTRL[1:0]
PLL_CP_GAIN[1:0]
09h
R28 (1Ch) PLL divider control 1
0
PLL_EXDIV_SEL[2:0]
PLL_FBDIV_SEL[3:0]
13h
R29 (1Dh) PLL divider control 2
0
0
PLL_POSTDIV2_SEL[1:0]
PLL_POSTDIV1_SEL[3:0]
13h
R35 (23h) Cycle mode control
0
0
0
0
INTM[1:0]
ACYC
LINBYLINE
00h
R37 (25h) DAC IN1
DACIN1[7:0]
80h
R38 (26h) DAC IN2
DACIN2[7:0]
80h
R40 (28h) DAC IN3
DACIN3[7:0]
80h
R41 (29h) DAC IN4
DACIN4[7:0]
80h
R43 (2Bh) DAC IN5
DACIN5[7:0]
80h
R44 (2Ch) DAC IN6
DACIN6[7:0]
80h
R46 (2Eh) AGAIN IN1
0
0
0
AGAININ1[4:0]
01h
R47 (2Fh) AGAIN IN2
0
0
0
AGAININ2[4:0]
01h
R49 (31h) AGAIN IN3
0
0
0
AGAININ3[4:0]
01h
R50 (32h) AGAIN IN4
0
0
0
AGAININ4[4:0]
01h
R52 (34h) AGAIN IN5
0
0
0
AGAININ5[4:0]
01h
R53 (35h) AGAIN IN6
0
0
0
AGAININ6[4:0]
01h
R56 (38h) DGAIN IN1 LSB
DGAININ1[3:0]
0
0
0
0
00h
R57 (39h) DGAIN IN1 MSB
DGAININ1[11:4]
80h



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