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WM8233 Datasheet(PDF) 68 Page - Cirrus Logic |
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WM8233 Datasheet(HTML) 68 Page - Cirrus Logic |
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68 / 146 page ![]() WM8233 68 Rev 4.7 Register 01h Chip ID 2 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION REFER TO R2 (02h) Chip Rev 3:0 CHIP_REV[3:0] 0000 A read returns the device revision number Register 02h Chip Rev REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION REFER TO R3 (03h) Setup Reg 1 4 ADC3PD 0 ADC powerdown control for channels 5&6 (related PGA and digits goes power down) 0 = normal operation 1 = power down 3 ADC2PD 0 ADC powerdown control for channels 3&4 (related PGA and digits goes power down) 0 = normal operation 1 = power down 2 ADC1PD 0 ADC powerdown control for channels 1&2 (related PGA and digits goes power down) 0 = normal operation 1 = power down 1 PDMD 0 power down mode 0 : standby 1 : sleep 0 PD 0 power down 0 : normal operation 1 : power down Register 03h Setup Reg 1 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION REFER TO R4 (04h) Setup Reg 2 7 VRLC _TOP_SEL 0 selects output range of VRLCDAC 0 = AVDD 1 = 1.6V 6 PGAFS 0 control PGA input polarity 0 = negative 1 = positive 5 ADCFS 0 control ADC full scale range 0 = 1.2V 1 = 1.8V 1 CLPMD 0 select clamp mode 0 = line clamp 1 = bit clamp 0 CDS 0 CDS mode control 0 = Non-CDS (S/H) mode 1 = CDS mode Register 04h Setup Reg 2 |
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