WM8233 datasheet(69/146 Pages) CIRRUS

69 / 146 page

WM8233

Rev 4.7

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

REFER TO

R5 (05h)

Setup Reg 3

SF_BYPLS

bypass level shift of VRLC source follower

0 = use level shifter

1 = bypass level shifter

3:2

PT_SF[1:0]

source follower power trim

00 = 1mA

01 = 2mA

10 = 3mA

11 = 4mA

SF_INP

control source follower on signal inputs INP*

0 = disabled

1 = enabled

SF_VRLC

control source follower on VRLC

0 = disabled

1 = enabled

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

REFER TO

R6 (06h)

VRLC control

VRLCEN

enable for VRLC DAC

0 = disabled

1 = enabled

6:5

VRLC_ISEL

[1:0]

selects output current capability

00 = Up to 2mA

01 = Up to 3mA

10 = Up to 4mA

11 = reserved (Up to 2mA)

4:0

VRLC_VSEL

[4:0]

0_1010

VRLC output voltage setting

when VRLC_TOP_SEL=0 (AVDD)

3.3/AVDD * ( 0.2 + 0.09xVRLC_VSEL[4:0])

when VRLC_TOP_SEL=1 (1.6V)

1.6 - 0.048*(31-VRLC_VSEL[4:0])

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

REFER TO

R7 (07h)

output control

OE_OP

output enable of dataout (CMOS/LVDS)

when HIZCTRL=0

0= Hi-Z

1= enable dataout

when HIZCTRL=1

OE_OP state is neglected and enable dataout

OUTPD

control data output

0 = enable data output

1 = mask data output (data out=0)

CMOSMODE

enable CMOS output mode

0 = LVDS output mode based on LVDSMODE[2:0]

1 = CMOS output mode

OUTSYNC

enable syncronous output mode

WM8233 Datasheet(PDF) 69 Page - Cirrus Logic

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