WM8233 datasheet(145/146 Pages) CIRRUS

145 / 146 page

WM8233

Rev 4.7

145

REVISION HISTORY

DATE

REV

ORIGINATOR

CHANGES

PAGE

13/10/2010

1.0

First Release

08/12/11

3.0

JMacD

Product status updated to pre-production,

10/12/11

3.0

Corrected DAC description 4-bit to 8bit

Corrected temperature range to -40

Corrected ADCFS characteristics

Corrected RLCDAC resolution

Corrected Parameter name and Register name for RLCDAC

Added test condition for TG output

Corrected Supply Currents

Corrected Clamp timing diagram

Corrected Signal flow summary (removed INVOP description)

Corrected Register Map (ADCFS)

5.8

9,10

10,38

38,48

Corrected Channel ID description INP to IN

Corrected TG MASK description

14/12/12

4.0

Added spec of channel to channel offset matching

Corrected RLCDAC resolution

Corrected offset DAC INL DNL spec

Corrected supply current for full power down mode

Updated timing specification

Added description for 3pair, 4pair LVDS mode

Added LVDS output order

Corrected figure for ADC INPUT BLACK LEVEL ADJUST

Corrected figure for overall signal flow

Added description for PLL DLL setup

Corrected TG timing diagram

Added EXTENDED REGISTERS

Corrected description for R28

Corrected description for R128,R129

16-18

26-28

31-33

50,118

72,73

07/02/13

4.1

Corrected missing description.

(ADC PGA Bias current control, PLL DLL setup, Output data

format)

21-30

17/02/14

4.2

Corrected description of conversion rate

Corrected description of reference DAC resolution

Updated test condition for output noise specification

Corrected device ID descriptions (Table 2 and Table 3)

Corrected RESET CLAMPING description

Corrected CDS/Non-CDS PROCESSING description

Updated PLL and DLL setting table

Corrected TG-master/slave mode timing chart

Added TGSYNC low period specification

Added description for LINE BY LINE operation

Added description for TEST PATTERN GENERATOR

Added description for Register setting procedure

13,14

17,18

34,35

48,58,74

49,50,71,72

51~57

22/05/14

4.3

Added data latency specification

Updated tPER, tMCLKH and tMCLKL description

Removed tPER and tMCLKD description

Removed tTRGD and tPCKD description

Updated Data trigger timing delay specification

Corrected TG MASK TIMING description

Added description of Data Output Configuration

Corrected register description of SEL_PCK7,8,9,10,11

32,34

59,60

98,99

WM8233 Datasheet(PDF) 145 Page - Cirrus Logic

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