DM505 datasheet(140/290 Pages) TI1

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Stop

Start

Repeated

Start

Stop

I2Ci_SDA

I2Ci_SCL

SPRS91v_I2C_01

140

DM505

SPRS976D – NOVEMBER 2016 – REVISED JULY 2017

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Specifications

Figure 5-32. I2C Receive Timing

Table 5-42 and Figure 5-33 assume testing over the recommended operating conditions and electrical

characteristic conditions below.

Table 5-42. Switching Characteristics Over Recommended Operating Conditions for I2C Output Timings(2)

NO.

PARAMETER

DESCRIPTION

STANDARD MODE

FAST MODE

UNIT

MIN

MAX

MIN

MAX

tc(SCL)

Cycle time, SCL

2.5

µs

tsu(SCLH-SDAL)

Setup time, SCL high before SDA low (for a

repeated START condition)

4.7

0.6

µs

th(SDAL-SCLL)

Hold time, SCL low after SDA low (for a

START and a repeated START condition)

0.6

µs

tw(SCLL)

Pulse duration, SCL low

4.7

1.3

µs

tw(SCLH)

Pulse duration, SCL high

0.6

µs

tsu(SDAV-SCLH)

Setup time, SDA valid before SCL high

250

100

th(SCLL-SDAV)

Hold time, SDA valid after SCL low (for I2C

bus devices)

3.45

0.9

µs

tw(SDAH)

Pulse duration, SDA high between STOP and

START conditions

4.7

1.3

µs

tr(SDA)

Rise time, SDA

1000

20 + 0.1Cb

(1)

300

tr(SCL)

Rise time, SCL

1000

20 + 0.1Cb

(1)

300

tf(SDA)

Fall time, SDA

300

20 + 0.1Cb

(1)

300

tf(SCL)

Fall time, SCL

300

20 + 0.1Cb

(1)

300

tsu(SCLH-SDAH)

Setup time, SCL high before SDA high (for

STOP condition)

0.6

µs

Capacitance for each I2C pin

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