Electronic Components Datasheet Search
  English  ▼

X  

AD9653 Datasheet(PDF) 11 Page - Analog Devices

Part # AD9653
Description  Analog-to-Digital Converter
PDF  42 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD9653 Datasheet(HTML) 11 Page - Analog Devices

Back Button AD9653 Datasheet HTML 7Page - Analog Devices AD9653 Datasheet HTML 8Page - Analog Devices AD9653 Datasheet HTML 9Page - Analog Devices AD9653 Datasheet HTML 10Page - Analog Devices AD9653 Datasheet HTML 11Page - Analog Devices AD9653 Datasheet HTML 12Page - Analog Devices AD9653 Datasheet HTML 13Page - Analog Devices AD9653 Datasheet HTML 14Page - Analog Devices AD9653 Datasheet HTML 15Page - Analog Devices Next Button
Zoom Inzoom in Zoom Outzoom out
 11 / 42 page
background image
AD9653
Data Sheet
Rev. E | Page 10 of 41
TIMING SPECIFICATIONS
Table 7.
Parameter
Description
Limit
Unit
SYNC TIMING REQUIREMENTS
tSSYNC
SYNC to rising edge of CLK+ setup time
1.2
ns min
tHSYNC
SYNC to rising edge of CLK+ hold time
−0.2
ns min
SPI TIMING REQUIREMENTS
See Figure 75
tDS
Setup time between the data and the rising edge of SCLK
2
ns min
tDH
Hold time between the data and the rising edge of SCLK
2
ns min
tCLK
Period of the SCLK
40
ns min
tS
Setup time between CSB and SCLK
2
ns min
tH
Hold time between CSB and SCLK
2
ns min
tHIGH
SCLK pulse width high
10
ns min
tLOW
SCLK pulse width low
10
ns min
tEN_SDIO
Time required for the SDIO pin to switch from an input to an output relative to the
SCLK falling edge (not shown in Figure 75)
10
ns min
tDIS_SDIO
Time required for the SDIO pin to switch from an output to an input relative to the
SCLK rising edge (not shown in Figure 75)
10
ns min
Timing Diagrams
Refer to the Memory Map Register Descriptions section and Table 23 for SPI register settings.
D0–A
D0+A
D1–A
D1+A
FCO–
BYTEWISE
MODE
FCO+
D0–A
D0+A
D1–A
D1+A
FCO–
DCO
DCO+
CLK+
VIN±x
CLK–
DCO–
FCO+
BITWISE
MODE
SDR
DDR
MSB
N – 17
D14
N – 17
D13
N – 17
D12
N – 17
D11
N – 17
D10
N – 17
D09
N – 17
D08
N – 17
MSB
N – 16
D14
N – 16
D13
N – 16
D12
N – 16
D11
N – 16
D10
N – 16
D09
N – 16
D08
N – 16
D07
N – 17
D06
N – 17
D05
N – 17
D04
N – 17
D03
N – 17
D02
N – 17
D01
N – 17
LSB
N – 17
D07
N – 16
D06
N – 16
D05
N – 16
D04
N – 16
D03
N – 16
D02
N – 16
D01
N – 16
LSB
N – 16
MSB
N – 17
D13
N – 17
D11
N – 17
D09
N – 17
D07
N – 17
D05
N – 17
D03
N – 17
D01
N – 17
MSB
N – 16
D13
N – 16
D11
N – 16
D09
N – 16
D07
N – 16
D05
N – 16
D03
N – 16
D01
N – 16
D14
N – 17
D12
N – 17
D10
N – 17
D08
N – 17
D06
N – 17
D04
N – 17
D02
N – 17
LSB
N – 17
D14
N – 16
D12
N – 16
D10
N – 16
D08
N – 16
D06
N – 16
D04
N – 16
D02
N – 16
LSB
N – 16
tA
tDATA
tLD
tEH
tFCO
tFRAME
tPD
tCPD
tEL
N – 1
N
N + 1
Figure 2. 16-Bit DDR/SDR, Two-Lane, 1× Frame Mode (Default)



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42


Datasheet Download

Go To PDF Page


Link URL



Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link to Datasheet    |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com