AD9653 datasheet(28/42 Pages) AD

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Data Sheet

AD9653

Rev. E | Page 27 of 41

ADC output driver supplies to avoid modulating the clock signal

with digital noise. Low jitter, crystal-controlled oscillators make

the best clock sources. If the clock is generated from another

type of source (by gating, dividing, or other methods), it should

be retimed by the original clock at the last step.

Refer to the AN-501 Application Note and the AN-756

Application Note for more in-depth information about jitter

performance as it relates to ADCs.

100

1000

16 BITS

14 BITS

12 BITS

100

110

120

130

0.125ps

0.25ps

0.5ps

1.0ps

2.0ps

ANALOG INPUT FREQUENCY (MHz)

10 BITS

8 BITS

RMS CLOCK JITTER REQUIREMENT

Figure 69. Ideal SNR vs. Input Frequency and Jitter

POWER DISSIPATION AND POWER-DOWN MODE

As shown in Figure 70, the power dissipated by the AD9653 is

proportional to its sample rate. The digital power dissipation

does not vary significantly because it is determined primarily by

the DRVDD supply and bias current of the LVDS output drivers.

0.20

0.25

0.30

0.35

0.40

0.45

0.50

0.55

0.60

100

120

SAMPLE RATE (MSPS)

VREF = 1.3V

VREF = 1.0V

Figure 70. Analog Core Power vs. fSAMPLE for fIN = 9.7 MHz, Four Channels

The AD9653 is placed in power-down mode either by the SPI

port or by asserting the PDWN pin high. In this state, the ADC

typically dissipates 2 mW. During power-down, the output

drivers are placed in a high impedance state. Asserting the

PDWN pin low returns the AD9653 to its normal operating

mode. Note that PDWN is referenced to the digital output

driver supply (DRVDD) and should not exceed that supply

voltage.

Low power dissipation in power-down mode is achieved by

shutting down the reference, reference buffer, biasing networks,

and clock. Internal capacitors are discharged when entering

power-down mode and then must be recharged when returning

to normal operation. As a result, wake-up time is related to the

time spent in power-down mode, and shorter power-down

cycles result in proportionally shorter wake-up times. When

using the SPI port interface, the user can place the ADC in

power-down mode or standby mode. Standby mode allows the

user to keep the internal reference circuitry powered when

faster wake-up times are required. See the Memory Map section

for more details on using these features.

DIGITAL OUTPUTS AND TIMING

The AD9653 differential outputs conform to the ANSI-644 LVDS

standard on default power-up. This can be changed to a low power,

reduced signal option (similar to the IEEE 1596.3 standard) via the

SPI. The LVDS driver current is derived on chip and sets the

output current at each output equal to a nominal 3.5 mA. A 100 Ω

differential termination resistor placed at the LVDS receiver

inputs results in a nominal 350 mV swing (or 700 mV p-p

differential) at the receiver.

When operating in reduced range mode, the output current is

reduced to 2 mA. This results in a 200 mV swing (or 400 mV p-p

differential) across a 100 Ω termination at the receiver.

The AD9653 LVDS outputs facilitate interfacing with LVDS

receivers in custom ASICs and FPGAs for superior switching

performance in noisy environments. Single point-to-point net

topologies are recommended with a 100 Ω termination resistor

placed as close to the receiver as possible. If there is no far-end

receiver termination or there is poor differential trace routing,

timing errors may result. To avoid such timing errors, it is

recommended that the trace length be less than 24 inches and

that the differential output traces be close together and at equal

lengths. An example of the FCO and data stream with proper

trace length and position is shown in Figure 71. Figure 72 shows

the LVDS output timing example in reduced range mode.

D0 500mV/DIV

D1 500mV/DIV

DCO 500mV/DIV

FCO 500mV/DIV

4ns/DIV

Figure 71. LVDS Output Timing Example in ANSI-644 Mode (Default)

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