AD9653 datasheet(30/42 Pages) AD

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Data Sheet

AD9653

Rev. E | Page 29 of 41

Data from each ADC is serialized and provided on a separate

channel in two lanes in DDR mode. The data rate for each serial

stream is equal to 16 bits times the sample clock rate divided by

the number of lanes, with a maximum of 1000 Mbps/lane

[(16 bits × 125 MSPS)/2 = 1000 Mbps/lane]. The maximum

allowable output data rate is 1 Gbps/lane. If one-lane mode is used,

the data rate doubles for a given sample rate. To stay within the

maximum data rate of 1 Gbps/lane, the sample rate is limited to a

maximum of 62.5 MSPS in one-lane output mode. The lowest

typical conversion rate is 20 MSPS.

Two output clocks are provided to assist in capturing data from

the AD9653. The DCO is used to clock the output data and is

equal to four times the sample clock (CLK) rate for the default

mode of operation. Data is clocked out of the AD9653 and must

be captured on the rising and falling edges of the DCO that

supports double data rate (DDR) capturing. The FCO is used to

signal the start of a new output byte and is equal to the sample

clock rate in 1× frame mode. See the Timing Diagrams section

for more information.

When the SPI is used, the DCO phase can be adjusted in 60°

increments relative one data cycle (30° relative to one DCO

cycle). This enables the user to refine system timing margins if

required. The default DCO+ and DCO− timing, as shown in

Figure 2, is 180° relative to one data cycle (90° relative to one

DCO cycle).

In default mode, as shown in Figure 2, the MSB is first in the

data output serial stream. This can be inverted so that the LSB

is first in the data output serial stream by using the SPI.

There are 12 digital output test pattern options available that

can be initiated through the SPI. This is a useful feature when

validating receiver capture and timing. Refer to Table 13 for the

output bit sequencing options available. Some test patterns have

two serial sequential words and can be alternated in various ways,

depending on the test pattern chosen. Note that some patterns

do not adhere to the data format select option. In addition,

custom user-defined test patterns can be assigned in the 0x19,

0x1A, 0x1B, and 0x1C register addresses.

Table 12. Digital Output Coding

Input (V)

Condition (V)

Offset Binary Output Mode

Twos Complement Mode

VIN+ − VIN−

<−VREF − 0.5 LSB

0000 0000 0000 0000

1000 0000 0000 0000

VIN+ − VIN−

−VREF

0000 0000 0000 0000

1000 0000 0000 0000

VIN+ − VIN−

0 V

1000 0000 0000 0000

0000 0000 0000 0000

VIN+ − VIN−

+VREF − 1.0 LSB

1111 1111 1111 1111

0111 1111 1111 1111

VIN+ − VIN−

>+VREF − 0.5 LSB

1111 1111 1111 1111

0111 1111 1111 1111

Table 13. Flexible Output Test Modes

Output Test

Mode Bit

Sequence

Pattern Name

Digital Output Word 1

Digital Output Word 2

Subject to

Data Format

Select

Notes

0000

Off (default)

Not applicable

0001

Midscale short

1000 0000 0000 0000 (16-bit)

Not applicable

Yes

Offset binary

code shown

0010

+Full-scale short

1111 1111 1111 1111 (16-bit)

Not applicable

Yes

Offset binary

code shown

0011

−Full-scale short

0000 0000 0000 0000 (16-bit)

Not applicable

Yes

Offset binary

code shown

0100

Checkerboard

1010 1010 1010 1010 (16-bit)

0101 0101 0101 0101 (16-bit)

0101

PN sequence long

Not applicable

Yes

PN23

ITU 0.150

X23 + X18 + 1

0110

PN sequence short

Not applicable

Yes

PN9

ITU 0.150

X9 + X5 + 1

0111

One-/zero-word

toggle

1111 1111 1111 1111 (16-bit)

0000 0000 0000 0000 (16-bit)

1000

User input

1001

1-/0-bit toggle

1010 1010 1010 1010 (16-bit)

Not applicable

1010

1× sync

0000 0000 1111 1111 (16-bit)

Not applicable

1011

One bit high

1000 0000 0000 0000 (16-bit)

Not applicable

Pattern

associated with

the external pin

1100

Mixed frequency

1010 0001 1001 1100 (16-bit)

Not applicable

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