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AD9653

Data Sheet

Rev. E | Page 30 of 41

The pseudorandom number (PN) sequence short pattern

produces a pseudorandom bit sequence that repeats itself every

29 − 1 or 511 bits. A description of the PN sequence and how it

is generated can be found in Section 5.1 of the ITU-T 0.150

(05/96) standard. The seed value is all 1s (see Table 14 for the

initial values). The output is a parallel representation of the serial

PN9 sequence in MSB-first format. The first output word is the

first 16 bits of the PN9 sequence in MSB aligned form.

The PN sequence long pattern produces a pseudorandom bit

sequence that repeats itself every 223 − 1 or 8,388,607 bits. A

description of the PN sequence and how it is generated can be

found in Section 5.6 of the ITU-T 0.150 (05/96) standard. The

seed value is all 1s (see Table 14 for the initial values) and the

AD9653 inverts the bit stream with relation to the ITU standard.

The output is a parallel representation of the serial PN23 sequence

in MSB-first format. The first output word is the first 16 bits of the

PN23 sequence in MSB aligned form

Table 14. PN Sequence

Sequence

Initial

Value

Next Three Output Samples

(MSB First) Twos Complement

PN Sequence Short

0x7F83

0x5F17, 0xB209, 0xCED1

PN Sequence Long

0x7FFF

0x7E00, 0x807C, 0x801F

Consult the Memory Map section for information on how to

change these additional digital output timing features through

the SPI.

SDIO/OLM Pin

For applications that do not require SPI mode operation, the

CSB pin is tied to AVDD, and the SDIO/OLM pin controls the

output lane mode according to Table 15.

Note that, when the CSB pin is tied to AVDD, the AD9653 DCS

is on by default and remains on unless the part is placed in SPI

mode and controlled via the SPI. Refer to the Clock Duty Cycle

section for more information on the DCS.

For applications where the SDIO/OLM pin is not used, CSB

should be tied to AVDD. When using the one-lane mode, the

conversion rate should be ≤62.5 MSPS to meet the maximum

output rate of 1 Gbps.

Table 15. Output Lane Mode Pin Settings

OLM Pin

Voltage

Output Mode

AVDD (Default)

Two-lane. 1× frame, 16-bit serial output

GND

One-lane. 1× frame, 16-bit serial output

SCLK/DTP Pin

The SCLK/DTP pin is used to select the digital test pattern

(DTP) for applications that do not require SPI mode operation.

This pin can enable a single digital test pattern if it and the CSB

pin are held high during device power-up. When SCLK/DTP is

tied to AVDD, the ADC channel outputs shift out the following

pattern: 1000 0000 0000 0000. The FCO and DCO function

normally while all channels shift out the repeatable test pattern.

This pattern allows the user to perform timing alignment

adjustments among the FCO, DCO, and output data. This pin has

an internal 10 kΩ resistor to GND. It can be left unconnected.

Table 16. Digital Test Pattern Pin Settings

Selected DTP

DTP Voltage

Resulting

D0±x and D1±x

Normal Operation

10 kΩ to AGND

Normal operation

DTP

AVDD

1000 0000 0000 0000

Additional and custom test patterns can also be observed when

commanded from the SPI port. Consult the Memory Map

section for information about the options available.

CSB Pin

The CSB pin should be tied to AVDD for applications that do

not require SPI mode operation. By tying CSB high, all SCLK

and SDIO information is ignored.

Note that when the CSB pin is tied to AVDD, the AD9653 DCS

is on by default and remains on unless the part is placed in SPI

mode and controlled via the SPI. Refer to the Clock Duty Cycle

section for more information on the DCS.

RBIAS Pin

To set the internal core bias current of the ADC, place a 10.0 kΩ,

1% tolerance resistor to ground at the RBIAS pin.

OUTPUT TEST MODES

The output test options are described in Table 13 and controlled by

the output test mode bits at Address 0x0D. When an output test

mode is enabled, the analog section of the ADC is disconnected

from the digital back-end blocks and the test pattern is run

through the output formatting block. Some of the test patterns

are subject to output formatting, and some are not. The PN

generators from the PN sequence tests can be reset by setting

Bit 4 or Bit 5 of Register 0x0D. These tests can be performed

with or without an analog signal (if present, the analog signal is

ignored), but they do require an encode clock. For more

information, see the AN-877 Application Note, Interfacing to

High Speed ADCs via SPI.

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