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AD9684

Data Sheet

FIR FILTERS

GENERAL DESCRIPTION

There are four sets of decimate by 2, low-pass, half-band, FIR

filters (labeled HB1 FIR, HB2 FIR, HB3 FIR, and HB4 FIR in

Figure 58) following the frequency translation stage. After the

carrier of interest is tuned down to dc (carrier frequency =

0 Hz), these filters efficiently lower the sample rate while

providing sufficient alias rejection from unwanted adjacent

carriers around the bandwidth of interest.

HB1 FIR is always enabled and cannot be bypassed. The HB2,

HB3, and HB4 FIR filters are optional and can be bypassed for

higher output sample rates.

Table 16 shows the different bandwidth options by including

different half-band filters. In all cases, the DDC filtering stage of

the AD9684 provides less than −0.001 dB of pass-band ripple

and greater than 100 dB of stop band alias rejection.

Table 17 shows the amount of stop band alias rejection for

multiple pass-band ripple/cutoff points. The decimation ratio of

the filtering stage of each DDC can be controlled individually

through Bits[1:0] of the DDC control registers (Register 0x310,

Table 16. DDC Filter Characteristics

ADC Sample

Rate (MSPS)

DDC Decimation

Ratio

Real Output

Sample Rate

(MSPS)

Complex (I/Q)

Output Sample

Rate (MSPS)

Alias Protected

Bandwidth

(MHz)

Ideal SNR

Improvement1

(dB)

Pass-Band

Ripple

(dB)

Alias

Rejection

(dB)

1000

2 (HB1)

1000

500 (I) + 500 (Q)

385.0

<−0.001

>100

4 (HB1 + HB2)

500

250 (I) + 250 (Q)

192.5

8 (HB1 + HB2 + HB3)

250

125 (I) + 125 (Q)

96.3

16 (HB1 + HB2 +

HB3 + HB4)

125

62.5 (I) + 62.5 (Q)

48.1

The ideal SNR improvement due to oversampling and filtering = 10log(bandwidth/(fS/2)).

Table 17. DDC Filter Alias Rejection

Alias Rejection (dB)

Pass-Band Ripple/Cutoff Point (dB)

Alias Protected Bandwidth for

Real (I) Outputs1

Alias Protected Bandwidth for

Complex (I/Q) Outputs1

>100

<−0.001

<38.5% × fOUT

<77% × fOUT

<−0.001

<38.7% × fOUT

<77.4% × fOUT

<−0.001

<38.9% × fOUT

<77.8% × fOUT

63.3

<−0.006

<40% × fOUT

<80% × fOUT

−0.5

44.4% × fOUT

88.8% × fOUT

19.3

−1.0

45.6% × fOUT

91.2% × fOUT

10.7

−3.0

48% × fOUT

96% × fOUT

fOUT = ADC input sample rate/DDC decimation ratio.

Rev. 0 | Page 40 of 64

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