AD9684 datasheet(28/65 Pages) AD

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Data Sheet

AD9684

CLOCK INPUT CONSIDERATIONS

For optimum performance, drive the AD9684 sample clock

inputs (CLK+ and CLK−) with a differential signal. This signal

is typically ac-coupled to the CLK+ and CLK− pins via a

transformer or clock drivers. These pins are biased internally

and require no additional biasing.

Figure 49 shows a preferred method for clocking the AD9684. The

low jitter clock source is converted from a single-ended signal to

a differential signal using an RF transformer.

ADC

CLK+

CLK–

0.1µF

100Ω

50Ω

CLOCK

INPUT

1:1Z

Figure 49. Transformer Coupled Differential Clock

Another option is to ac couple a differential CML or LVDS

signal to the sample clock input pins, as shown in Figure 50 and

Figure 51.

ADC

CLK+

CLK–

0.1µF

Z0 = 50Ω

33Ω

71Ω

10pF

3.3V

Figure 50. Differential CML Sample Clock

ADC

CLK+

CLK–

0.1µF

50Ω1

100Ω

CLOCK INPUT

LVDS

DRIVER

CLK+

CLK–

50Ω RESISTORS ARE OPTIONAL.

CLOCK INPUT

Figure 51. Differential LVDS Sample Clock

Clock Duty Cycle Considerations

Typical high speed ADCs use both clock edges to generate a

variety of internal timing signals. As a result, these ADCs may

be sensitive to the clock duty cycle. Commonly, a 5% tolerance

is required on the clock duty cycle to maintain dynamic performance

characteristics. In applications where the clock duty cycle cannot

be guaranteed to be 50%, a higher multiple frequency clock can be

supplied to the device. The AD9684 can be clocked at 2 GHz with

the internal clock divider set to 2. The output of the divider offers

a 50% duty cycle, high slew rate (fast edge) clock signal to the

internal ADC. See the Memory Map section for more details on

using this feature.

Input Clock Divider

The AD9684 contains an input clock divider with the ability to

divide the Nyquist input clock by 1, 2, 4, and 8. The divider

ratios can be selected using Register 0x10B. This is shown in

Figure 52.

The maximum frequency at the CLK± inputs is 4 GHz. This is

the limit of the divider. In applications where the clock input is

a multiple of the sample clock, the appropriate divider ratio

must be programmed into the clock divider before applying the

clock signal. This ensures that the current transients during

device startup are controlled.

CLK+

CLK–

÷2

÷4

REG 0x10B

÷8

Figure 52. Clock Divider Circuit

The AD9684 clock divider can be synchronized using the external

SYNC± input. A valid SYNC± input causes the clock divider to

reset to a programmable state. This feature is enabled by setting

Bit 7 of Register 0x10D. This synchronization feature allows

multiple devices to have their clock dividers aligned to guarantee

simultaneous input sampling.

Input Clock Divider ½ Period Delay Adjustment

The input clock divider inside the AD9684 provides phase delay

in increments of ½ the input clock cycle. Program Register 0x10C

to enable this delay independently for each channel.

Clock Fine Delay Adjustment

To adjust the AD9684 sampling edge instant, write to Register 0x117

and Register 0x118. Setting Bit 0 of Register 0x117 enables the fine

delay feature, and Register 0x118, Bits[7:0] set the value of the

delay. This value can be programmed individually for each channel.

The clock delay can be adjusted from −151.7 ps to +150 ps in

~1.7 ps increments. The clock delay adjust takes effect immediately

when it is enabled via SPI writes. Enabling the clock fine delay

adjustment in Register 0x117 causes a datapath reset.

Clock Jitter Considerations

High speed, high resolution ADCs are sensitive to the quality of

the clock input. The degradation in SNR at a given input

frequency (fA) due only to aperture jitter (tJ) can be calculated by

SNR = 20 × log 10 (2 × π × fA × tJ)

In this equation, the rms aperture jitter represents the root mean

square of all jitter sources, including the clock input, analog input

signal, and ADC aperture jitter specifications. IF undersampling

applications are particularly sensitive to jitter (see Figure 53).

Rev. 0 | Page 27 of 64

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