AD9684

Data Sheet

Chip

Application

Layer

Chip

Decimation

Ratio

DDC Input

Type

DDC

Output

Type

Bandwidth

Per DDC1

Number of Virtual

Converters

Required (M)

Register Settings2

Register 0x351 = 0x05 (DDC 2 I input =

ADC Channel B, DDC 2 Q input = ADC

Channel B)

Register 0x371 = 0x05 (DDC 3 I input =

ADC Channel B, DDC 3 Q input = ADC

Channel B)

Register 0x314, 0x315, 0x320, 0x321 =

FTW and POW set as required by

application for DDC 0

Register 0x334, Register 0x335,

Register 0x340, Register 0x341 = FTW

and POW set as required by application

for DDC 1

Register 0x354, Register 0x355,

Register 0x360, Register 0x361 = FTW

and POW set as required by application

for DDC 2

Register 0x374, Register 0x375,

Register 0x380, Register 0x381 = FTW

and POW set as required by application

for DDC 3

1

2

The NCOs must be synchronized either through the SPI or through the SYNC± pins after all writes to the FTW or POW registers are complete. This ensures the proper

operation of the NCO. See the NCO Synchronization section for more information.

Rev. 0 | Page 46 of 64