AD9684 datasheet(48/65 Pages) AD

48 / 65 page

Data Sheet

AD9684

DIGITAL OUTPUTS

The AD9684 output drivers are for standard ANSI LVDS, but

optionally the drive current can be reduced using Register 0x56A.

The reduced drive current for the LVDS outputs potentially

reduces the digitally induced noise.

As detailed in the AN-877 Application Note, Interfacing to High

Speed ADCs via SPI, the data format can be selected for offset

binary, twos complement, or gray code when using the SPI

control.

The AD9684 has a flexible three-state ability for the digital

output pins. The three-state mode is enabled when the device is

set for power-down mode.

As shown in Table 24, the function of the output pins changes

based upon the selection of either parallel or byte output mode

in Register 0x568.

Timing

The AD9684 provides latched data with a pipeline delay of

33 input sample clock cycles. Data outputs are available one

propagation delay (tPD) after the rising edge of the clock signal.

Minimize the length of the output data lines and the corresponding

loads to reduce transients within the AD9684. These transients

can degrade converter dynamic performance.

The lowest typical conversion rate of the AD9684 is 250 MSPS.

At clock rates below 250 MSPS, dynamic performance may

degrade.

Data Clock Output

The AD9684 also provides a data clock output (DCO) intended

for capturing the data in an external register. The DCO relative

to the data output can be adjusted using Register 0x569.

ADC OVERRANGE

The ADC overrange (OR) indicator is asserted when an overrange

is detected on the input of the ADC. The overrange condition is

determined at the output of the ADC pipeline and, therefore, is

subject to a latency of 28 ADC clocks. An overrange at the input is

indicated by the OR bit 28 clock cycles after it occurs.

Table 23. LVDS Output Configurations

Parallel Output Mode

Number of Virtual

Converters Supported

Virtual Converter

Resolution (Max)

LVDS Byte Mode Outputs Required

Parallel Interleaved, Two

Converters (0x1)

14-bit

DCO + STATUS + D[13:0]

Parallel Channel Multiplexed, Two

Converters (0x3)

14-bit

DCO + STATUS + D[13:7] =

Channel AD[6:0] = Channel B

Byte Mode, Two Converters (0x5)

16-bit

1 DCO + 1 STATUS + 8 DATA[7:0]

Byte Mode, Four Converters (0x6)

16-bit

1 DCO + 1 STATUS + 8 DATA[7:0]

Byte Mode, Eight Converters (0x7)

16-bit

1 DCO + 1 STATUS + 8 DATA[7:0]

Table 24. Pin Mapping Between LVDS Parallel/Byte Modes

Pin Name

LVDS Parallel Mode Output

LVDS Byte Mode Output

DCO−, DCO+

STATUS−, STATUS+

OVR−, OVR+

FCO−, FCO+

D13−, D13+

STATUS−, STATUS+

D12−, D12+

DATA7−, DATA7+

D11−, D11+

DATA6−, DATA6+

D10−, D10+

DATA5−, DATA5+

D9−, D9+

DATA4−, DATA4+

D8−, D8+

DATA3−, DATA3+

D7−, D7+

DATA2−, DATA2+

D6−, D6+

DATA1−, DATA1+

D5−, D5+

DATA0−, DATA0+

D4−, D4+

Not applicable

D3−, D3+

Not applicable

D2−, D2+

Not applicable

D1−, D1+

Not applicable

D0−, D0+

Not applicable

Rev. 0 | Page 47 of 64

AD9684 Datasheet(PDF) 48 Page - Analog Devices

AD9684 Datasheet(HTML) 48 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65

Datasheet Download

Link URL