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AD9684 Datasheet(PDF) 57 Page - Analog Devices |
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AD9684 Datasheet(HTML) 57 Page - Analog Devices |
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57 / 65 page  AD9684 Data Sheet Reg. Addr. (Hex) Register Name Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB) Default Notes 0x118 Clock fine delay (local) Clock fine delay adjust, Bits[7:0] Twos complement coded control to adjust the fine sample clock skew in ~1.7 ps steps ≤−88 = −151.7 ps skew −87 = −150 ps skew … 0 = 0 ps skew … ≥+87 = +150 ps skew 0x00 Used in con- junction with Reg. 0x0117 0x11C Clock status 0 0 0 0 0 0 0 0 = no input clock detected 1 = input clock det- ected 0x00 Read only 0x120 SYNC± Control 1 0 SYNC± flag reset 0 = normal operation 1 = flags held in reset 0 SYNC± transition select 0 = low to high 1 = high to low CLK± edge select 0 = rising 1 = falling SYNC± mode select 00 = disabled 01 = continuous 10 = N shot 0 0x00 0x121 SYNC± Control 2 0 0 0 0 SYNC± N shot ignore counter select 0000 = next SYNC± only 0001 = ignore the first SYNC± transitions 0010 = ignore the first two SYNC± transitions … 1111 = ignore the first 16 SYNC± transitions 0x00 Mode select (Reg. 0x120, Bits[2:1]) must be N shot 0x123 SYNC± timestamp delay control SYNC± timestamp delay, Bits[6:0] 0x00 = no delay 0x01 = 1 clock delay … 0x7F = 127 clocks delay 0x00 Ignored when Reg. 0x01FF = 0x00 0x128 SYNC± Status 1 SYNC± hold status, Register 0x128, Bits [7:4] SYNC± setup status, Register 0x128, Bits [3:0] Read only 0x129 SYNC± and clock divider status 0 0 0 0 Clock divider phase when SYNC± was captured 0000 = in-phase 0001 = SYNC± is ½ cycle delayed from clock 0010 = SYNC± is 1 cycle delayed from clock 0011 = 1½ input clock cycles delayed 0100 = 2 input clock cycles delayed 0101 = 2½ input clock cycles delayed … 1111 = 7½ input clock cycles delayed Read only 0x12A SYNC± counter SYNC± counter, Bits[7:0] increments when a SYNC± signal is captured Read only 0x1FF Chip sync mode Synchronization mode 00 = normal 01 = timestamp 0x00 0x200 Chip application mode 0 0 Chip Q ignore 0 = normal (I/Q) 1 = ignore (I only) 0 0 0 Chip operating mode 00 = full bandwidth mode 01 = DDC 0 on 10 = DDC 0 and DDC 1 0x00 0x201 Chip decimation ratio 0 0 0 0 0 Chip decimation ratio select 000 = decimate by 1 001 = decimate by 2 010 = decimate by 4 011 = decimate by 8 100 = decimate by 16 0x00 0x228 Customer offset Offset adjust in LSBs from +127 to −128 (twos complement format) 0x00 Rev. 0 | Page 56 of 64 |
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