AD9684 datasheet(27/65 Pages) AD

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AD9684

Data Sheet

Table 9 shows the recommended buffer current and full-scale

voltage settings for the different analog input frequency ranges.

Absolute Maximum Input Swing

The absolute maximum input swing allowed at the inputs of the

AD9684 is 4.3 V p-p differential. Signals operating near or at

this level can cause permanent damage to the ADC.

VOLTAGE REFERENCE

A stable and accurate 1.0 V voltage reference is built into the

AD9684. This internal 1.0 V reference sets the full-scale input

range of the ADC. For more information on adjusting the input

swing, see Table 29. Figure 46 shows the block diagram of the

internal 1.0 V reference controls.

ADC

CORE

FULL-SCALE

VOLTAGE

ADJUST

V_1P0 PIN

CONTROL SPI

(REGISTER 0x024)

V_1P0

VIN–A/

VIN–B

VIN+A/

VIN+B

INTERNAL

V_1P0

GENERATOR

INPUT FULL-SCALE

RANGE ADJUST

SPI REGISTER

(REGISTER 0x025)

Figure 46. Internal Reference Configuration and Controls

reference, or to provide an external 1.0 V reference. When using

an external voltage reference, provide a 1.0 V reference. The

full-scale adjustment is made using the SPI, irrespective of the

reference voltage. For more information on adjusting the full-

scale level of the AD9684, see the Memory Map Register Table

section.

The use of an external reference may be necessary, in some

applications, to enhance the gain accuracy of the ADC or

improve thermal drift characteristics. Figure 47 shows the

typical drift characteristics of the internal 1.0 V reference.

–50

TEMPERATURE (°C)

0.9998

0.9999

1.0000

1.0001

1.0002

1.0003

1.0004

1.0005

1.0006

1.0007

1.0008

1.0009

1.0010

Figure 47. Typical V_1P0 Drift

The external reference must be a stable 1.0 V reference. The

ADR130 is a good option for providing the 1.0 V reference.

Figure 48 shows how the ADR130 can be used to provide the

external 1.0 V reference to the AD9684. The grayed out areas

show unused blocks within the AD9684 while using the

ADR130 to provide the external reference.

Table 9. SFDR Optimization for Input Frequencies

Frequency

Buffer Control 1

(Register 0x018)

Input Full-Scale Range

(Register 0x025)

Input Full-Scale Control

(Register 0x030)

Input Termination

(Register 0x016)1

DC to 250 MHz

0x20 (2.0×)

0x0C (2.06 V p-p)

0x04

0x0C/0x1C/0x6C

250 MHz to 500

MHz

0x70 (4.5×)

0x0C (2.06 V p-p)

0x04

0x0C/0x1C/0x6C

500 MHz to

1 GHz

0x80 (5.0×)

0x08 (1.46 V p-p)

0x18

0x0C/0x1C/0x6C

1 GHz to 2 GHz

0xF0 (8.5×)

0x08 (1.46 V p-p)

0x18

0x0C/0x1C/0x6C

The input termination can be changed to accommodate the application with little or no impact to ac performance.

FULL-SCALE

VOLTAGE

ADJUST

V_1P0

0.1µF

VOUT 4

SET

VIN

GND

ADR130

0.1µF

INPUT

FULL-SCALE

CONTROL

INTERNAL

V_1P0

GENERATOR

Figure 48. External Reference Using the ADR130

Rev. 0 | Page 26 of 64

AD9684 Datasheet(PDF) 27 Page - Analog Devices

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