AD9684 datasheet(56/65 Pages) AD

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Data Sheet

AD9684

Reg.

Addr.

(Hex)

Name

Bit 7

(MSB)

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0 (LSB)

Default

Notes

0x028

Tempera-

ture diode

(local)

Diode

selection

0 = no

diode

selected

1 =

tempera-

ture diode

selected

0x00

Used in

conjunc-

tion with

Reg. 0x040

0x030

Input full-

scale

control

(local)

Full-scale control

See Table 9 for

recommended settings for

different frequency bands

Default values:

Full scale range ≥ 1.82 V =

001

Full scale range < 1.82 V =

110

0x04

Input full-

scale

control

(local)

0x03F

PDWN/

STBY pin

control

(local)

0 =

PDWN/

STBY

enabled

1 =

disabled

0x00

Used in

conjunc-

tion with

Reg. 0x040

0x040

Chip pin

control

PDWN/STBY function

00 = power down

01 = standby

10 = disabled

Fast Detect B (FD_B)

000 = Fast Detect B output

001 = reserved

010 = reserved

111 = disabled

Fast Detect A (FD_A)

000 = Fast Detect A output

001 = reserved

010 = reserved

011 = temperature diode

111 = disabled

0x3F

0x10B

Clock

divider

000 = divide by 1

001 = divide by 2

011 = divide by 4

111 = divide by 8

0x00

0x10C

Clock

divider

phase

(local)

Independently controls Channel A and Channel B

clock divider phase offset

0000 = 0 input clock cycles delayed

0001 = ½ input clock cycles delayed

0010 = 1 input clock cycles delayed

0011 = 1½ input clock cycles delayed

0100 = 2 input clock cycles delayed

0101 = 2½ input clock cycles delayed

…

1111 = 7½ input clock cycles delayed

0x00

0x10D

Clock

divider and

SYNC±

control

Clock

divider

automatic

phase

adjustment

0 =

disabled

1 =

enabled

Clock divider negative

skew window

00 = no negative skew

01 = 1 device clock of

negative skew

10 = 2 device clocks of

negative skew

11 = 3 device clocks of

negative skew

Clock divider positive

skew window

00 = no positive skew

01 = 1 device clock of

positive skew

10 = 2 device clocks of

positive skew

11 = 3 device clocks of

positive skew

0x00

Clock

divider

must be

0x117

Clock delay

control

Clock fine

delay

adjust

enable

0 =

disabled

1 =

enabled

0x00

Enabling

the clock

fine delay

adjustment

causes a

datapath

soft reset

Rev. 0 | Page 55 of 64

AD9684 Datasheet(PDF) 56 Page - Analog Devices

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