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Data Sheet

AD9684

CLK+

DCO± (DATA CLOCK OUTPUT)

0° PHASE ADJUST

DCO± (DATA CLOCK OUTPUT)

180° PHASE ADJUST

SYNC+

APERTURE DELAY

N + x

N + 36

N + 37

N + 38

VIN±x

CLK–

SYNC–

tCLK

tDCO

tPD

SYNCHRONOUS LOW TO HIGH TRANSITIONS OF THE SYNC SIGNAL CAPTURED ON THE RISING EDGE OF

THE CLK SIGNAL CAUSES THE DCO INTERNAL DIVIDER TO BE RESET

CHANNEL A D12±/D13±

CHANNEL A D0±/D1±

CONVERTERS

SAMPLE

[N]

S[N – y]

(ODD BITS)

S[N]

(ODD BITS)

S[N – x]

(EVEN BITS)

S[N]

(EVEN BITS)

S[N + 1]

(ODD BITS)

S[N + 1]

(EVEN BITS)

S[N + 2]

(EVEN BITS)

STATUS

STATUS–

STATUS+

(OVERRANGE/STAUS BIT)

CONVERTERS

SAMPLE

[N]

CONVERTERS

SAMPLE

[N + 1]

CONVERTERS

SAMPLE

[N + 1]

CONVERTERS

SAMPLE

[N + 2]

S[N – 1]

(ODD BITS)

tSKEWF

tSKEWR

STATUS BIT SELECTED BY

IN THE REGISTER MAP

CONSTANT LATENCY = X CLK CYCLES

Figure 6. Channel Multiplexed (Even/Odd) Mode—One Converter, ≤14-Bit Data

Rev. 0 | Page 11 of 64

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