AD9684 datasheet(59/65 Pages) AD

59 / 65 page

AD9684

Data Sheet

Reg.

Addr.

(Hex)

Name

Bit 7

(MSB)

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0 (LSB)

Default

Notes

0x275

Signal

Monitor

Result

(local)

Signal monitor result, Bits[7:0]

When Register 0x0274, Bit 0 = 1, result Bits[19:7] = peak detector absolute value, Bits [12:0]; result Bits[6:0] = 0

Read

only

Updated

based on

Reg. 0x274,

Bit 4

0x276

Signal

Monitor

Result

(local)

Signal monitor result, Bits[15:8]

Read

only

Updated

based on

Reg.

0x274, Bit 4

0x277

Signal

Monitor

Result

(local)

Signal monitor result, Bits[19:16]

Read

only

Updated

based on

Reg.

0x274, Bit 4

0x278

Signal

monitor

period

counter

result

(local)

Period count result, Bits[7:0]

Read

only

Updated

based on

Reg.

0x274, Bit 4

Digital Downconverter (DDC) Function Registers—See the Digital Downconverters (DDCs) Section

0x300

DDC syn-

chronization

control

DDC NCO

soft reset

0 = normal

operation

1 = reset

Synchronization mode

(triggered by SYNC±)

00 = disabled

01 = continuous

11 = one-shot

0x310

DDC 0

control

Mixer

select

0 = real

mixer

1 =

complex

mixer

Gain select

0 = 0 dB

gain

1 = 6 dB

gain

IF mode

00 = variable IF mode

(mixers and NCO

enabled)

01 = 0 Hz IF mode (mixer

bypassed, NCO disabled)

10 = fS/4 Hz IF mode (fS/4

downmixing mode)

11 = test mode (mixer

inputs forced to +FS,

NCO enabled)

Complex to

real enable

0 = disabled

1 = enabled

Decimation rate select

(complex to real

disabled)

11 = decimate by 2

00 = decimate by 4

01 = decimate by 8

10 = decimate by 16

(complex to real

enabled)

11 = decimate by 1

00 = decimate by 2

01 = decimate by 4

10 = decimate by 8

0x00

0x311

DDC 0

input

selection

Q input

select

0 = Ch. A

1 = Ch. B

I input

select

0 = Ch. A

1 = Ch. B

0x00

0x314

DDC 0

frequency

LSB

DDC 0 NCO FTW, Bits[7:0], twos complement

0x00

0x315

DDC 0

frequency

MSB

DDC 0 NCO FTW, Bits[11:8], twos complement

0x00

0x320

DDC 0

phase LSB

DDC 0 NCO POW, Bits[7:0], twos complement

0x00

0x321

DDC 0

phase MSB

DDC 0 NCO POW, Bits[11:8], twos complement

0x00

0x327

DDC 0

output test

mode

selection

Q output

test mode

enable

0 =

disabled

1 = enabled

from Ch. B

I output

test mode

enable

0 =

disabled

1 =

enabled

from Ch. A

0x00

Rev. 0 | Page 58 of 64

AD9684 Datasheet(PDF) 59 Page - Analog Devices

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