AD9689 datasheet(109/134 Pages) AD

109 / 134 page

Data Sheet

AD9689

Rev. A | Page 109 of 134

Addr.

Name

Bit(s) Bit Name

Setting

Description

Reset

Access

DDC1 complex to real

enable

0x0

R/W

Complex (I and Q) outputs contain valid data.

Real (I) output only. Complex to real enabled. Uses extra fS mixing

to convert to real.

[2:0] DDC1 decimation rate

select

Decimation filter selection.

0x0

R/W

000

HB1 + HB2 filter selection: decimate by 2 (complex to real

enabled), or decimate by 4 (complex to real disabled).

001

HB1 + HB2 + HB3 filter selection: decimate by 4 (complex to real

enabled), or decimate by 8 (complex to real disabled).

010

HB1 + HB2 + HB3 + HB4 filter selection: decimate by 8 (complex

to real enabled), or decimate by 16 (complex to real disabled).

011

HB1 filter selection: decimate by 1 (complex to real enabled), or

decimate by 2 (complex to real disabled).

100

HB1 + TB2 filter selection: decimate by 3 (complex to real

enabled), or decimate by 6 (complex to real disabled).

101

HB1 + HB2 + TB2 filter selection: decimate by 6 (complex to real

enabled), or decimate by 12 (complex to real disabled).

110

HB1 + HB2 + HB3 + TB2 filter selection: decimate by 12 (complex

to real enabled), or decimate by 24 (complex to real disabled).

111

Decimation determined by Register 0x0331, Bits[7:4].

0x0331 DDC1 input

select

[7:4] DDC1 decimation rate

select

Only valid when Register 0x0310, Bits[2:0] = 3'b111.

0x0

R/W

0000

TB2 + HB4 + HB3 + HB2 + HB1 filter selection: decimate by 48

(complex to real disabled), or decimate by 24 (complex to real

enabled).

0010

FB2 + HB1 filter selection: decimate by 10 (complex to real

disabled), or decimate by 5 (complex to real enabled).

0011

FB2 + HB2 + HB1 filter selection: decimate by 20 (complex to real

disabled), or decimate by 10 (complex to real enabled).

0100

FB2 + HB3 + HB2 + HB1 filter selection: decimate by 40 (complex

to real disabled), or decimate by 20 (complex to real enabled).

0111

TB1 filter selection: decimate by 3 (decimate by 1.5 not

supported).

1000

FB2 + TB1 filter selection: decimate by 15 (decimate by 7.5 not

supported).

1001

HB2 + FB2 + TB1 filter selection: decimate by 30 (decimate by 15

not supported).

Reserved

Reserved.

0x0

DDC1 Q input select

0x1

R/W

Channel A.

Channel B.

Reserved

Reserved.

0x0

DDC1 I input select

0x1

R/W

Channel A.

Channel B.

0x0334 DDC1 NCO

control

[7:4] DDC1 NCO channel

select mode

For edge control, the internal counter wraps when the

0x0

R/W

0000

Use Register 0x0334, Bits[3:0].

0001

PIO_B0, GPIO_A0.

0010

GPIO_B1, GPIO_A1.

0011

GPIO_A1, GPIO_A0.

0100

GPIO_B1, GPIO_B0.

0101

GPIO_B1, GPIO_A1, GPIO_B0, GPIO_A0.

0110

GPIO_B1, GPIO_B0, GPIO_A1, GPIO_A0.

1000

Increment internal counter on rising edge of the GPIO_A0 pin.

1001

Increment internal counter on rising edge of the GPIO_A1 pin.

1010

Increment internal counter on rising edge of the GPIO_B0 pin.

1011

Increment internal counter on rising edge of the GPIO_B1 pin.

AD9689 Datasheet(PDF) 109 Page - Analog Devices

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