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AD9627 Datasheet(PDF) 41 Page - Analog Devices |
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AD9627 Datasheet(HTML) 41 Page - Analog Devices |
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41 / 77 page  AD9627 Rev. B | Page 40 of 76 CHANNEL/CHIP SYNCHRONIZATION The AD9627 has a SYNC input that offers the user flexible synchronization options for synchronizing the internal blocks. The clock divider sync feature is useful for guaranteeing synchro- nized sample clocks across multiple ADCs. The signal monitor block can also be synchronized using the SYNC input, allowing properties of the input signal to be measured during a specific time period. The input clock divider can be enabled to synchronize on a single occurrence of the SYNC signal or on every occurrence. The signal monitor block is synchronized on every SYNC input signal. The SYNC input is internally synchronized to the sample clock; however, to ensure there is no timing uncertainty between multiple parts, the SYNC input signal should be externally synchronized to the input clock signal, meeting the setup and hold times shown in Table 8. The SYNC input should be driven using a single- ended CMOS-type signal. |
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