AD9627 datasheet(13/77 Pages) AD

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AD9627

Rev. B | Page 12 of 76

SWITCHING SPECIFICATIONS—AD9627-125/AD9627-150

AVDD = 1.8 V, DVDD = 1.8 V, DRVDD = 3.3 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, and

DCS enabled, unless otherwise noted.

Table 7.

Parameter

Temperature

AD9627-125

AD9627-150

Unit

Min

Typ

Max

Min

Typ

Max

CLOCK INPUT PARAMETERS

Input Clock Rate

Full

625

MHz

Conversion Rate

DCS Enabled1

Full

125

150

MSPS

DCS Disabled1

Full

125

150

MSPS

CLK Period—Divide-by-1 Mode (tCLK)

Full

6.66

CLK Pulse Width High

Divide-by-1 Mode, DCS Enabled

Full

2.4

5.6

2.0

3.33

4.66

Divide-by-1 Mode, DCS Disabled

Full

3.6

4.4

3.0

3.33

3.66

Divide-by-2 Mode, DCS Enabled

Full

1.6

Divide-by-3-Through-8 Mode,

DCS Enabled

Full

0.8

DATA OUTPUT PARAMETERS (DATA, FD)

CMOS Mode—DRVDD = 3.3 V

Data Propagation Delay (tPD)2

Full

2.2

4.5

6.4

2.2

4.5

6.4

DCO Propagation Delay (tDCO)

Full

3.8

5.0

6.8

3.8

5.0

6.8

Setup Time (tS)

Full

4.5

3.83

Hold Time (tH)

Full

3.5

2.83

CMOS Mode—DRVDD = 1.8 V

Data Propagation Delay (tPD)2

Full

2.4

5.2

6.9

2.4

5.2

6.9

DCO Propagation Delay (tDCO)

Full

4.0

5.6

7.3

4.0

5.6

7.3

Setup Time (tS)

Full

4.4

3.73

Hold Time (tH)

Full

3.6

2.93

LVDS Mode—DRVDD = 1.8 V

Data Propagation Delay (tPD)2

Full

2.0

4.8

6.3

2.0

4.8

6.3

DCO Propagation Delay (tDCO)

Full

5.2

7.3

9.0

5.2

7.3

9.0

CMOS Mode Pipeline Delay (Latency)

Full

Cycles

LVDS Mode Pipeline Delay (Latency)

Channel A/Channel B

Full

12/12.5

Cycles

Aperture Delay (tA)

Full

1.0

Aperture Uncertainty (Jitter, tJ)

Full

0.1

ps rms

Wake-Up Time3

Full

350

μs

OUT-OF-RANGE RECOVERY TIME

Full

Cycles

1 Conversion rate is the clock rate after the divider.

2 Output propagation delay is measured from CLK 50% transition to DATA 50% transition, with 5 pF load.

3 Wake-up time is dependent on the value of the decoupling capacitors.

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