AD9627 datasheet(49/77 Pages) AD

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AD9627

Rev. B | Page 48 of 76

Increase Gain Dwell Time (Register 0x10A and

[7:0]

These registers are programmed with the dwell time in ADC

clock cycles for which the signal must be below the fine lower

threshold value before the increase gain output is asserted.

Signal Monitor DC Correction Control (Register 0x10C)

Bit 7—Reserved

Bit 6—DC Correction Freeze

When Bit 6 is set high, the dc correction is no longer updated

to the signal monitor block. It holds the last dc value it calculated.

Bits[5:2]—DC Correction Bandwidth

These bits set the averaging time of the power monitor dc

correction function. This 4-bit word sets the bandwidth of the

correction block according to the following equation:









CLK

Corr

where:

k is the 4 bit value programmed in Register 0x10C, Bits[5:2]

(values between 0 and 13 are valid for k; programming 14 or

15 provides the same result as programming 13).

fCLK is the AD9627 ADC sample rate in hertz (Hz).

Bit 1—DC Correction for Signal Path Enable

Setting Bit 1 high causes the output of the dc measurement

block to be summed with the data in the signal path to remove

the dc offset from the signal path.

Bit 0—DC Correction for Signal Monitor Enable

Bit 0 enables the dc correction function in the signal monitor block.

The dc correction is an averaging function that can be used by

the signal monitor to remove dc offset in the signal. Removing

this dc offset from the measurement allows a more accurate

reading.

Signal Monitor DC Value Channel A (Register 0x10D and

These read-only registers hold the latest dc offset value computed

by the signal monitor for Channel A.

Signal Monitor DC Value Channel B (Register 0x10F and

These read-only registers hold the latest dc offset value computed

by the signal monitor for Channel B.

Signal Monitor SPORT Control (Register 0x111)

Bit 7—Reserved

Bit 6—RMS/MS Magnitude Output Enable

These bits enable the 20-bit rms or ms magnitude measurement

as output on the SPORT.

Bit 5—Peak Detector Output Enable

Bit 5 enables the 13-bit peak measurement as output on the

SPORT.

Bit 4—Threshold Crossing Output Enable

Bit 4 enables the 13-bit threshold measurement as output on

the SPORT.

Bits[3:2]—SPORT SMI SCLK Divide

The values of these bits set the SPORT SMI SCLK divide ratio

from the input clock. A value of 0x01 sets divide by 2 (default),

a value of 0x10 sets divide by 4, and a value of 0x11 sets divide by 8.

Bit 1— SPORT SMI SCLK Sleep

Setting Bit 1 high causes the SMI SCLK to remain low when the

signal monitor block has no data to transfer.

Bit 0—Signal Monitor SPORT Output Enable

When set, Bit 0 enables the SPORT output of the signal monitor

to begin shifting out the result data from the signal monitor block.

Signal Monitor Control (Register 0x112)

Bit 7—Complex Power Calculation Mode Enable

This mode assumes I data is present on one channel and Q data

is present on the alternate channel. The result reported is the

complex power, measured as

I 

Bits[6:4]—Reserved

Bit 3—Signal Monitor RMS/MS Select

Setting Bit 3 low selects rms power measurement mode. Setting

Bit 3 high selects ms power measurement mode.

Bits[2:1]—Signal Monitor Mode

Bit 2 and Bit 1 set the mode of the signal monitor for data output

to Register 0x116 through Register 0x11B. Setting Bit 2 and Bit 1

to 0x00 selects rms/ms magnitude output; setting these bits to

0x01 selects peak detector output; and setting these bits to 0x10

or 0x11 selects threshold crossing output.

Bit 0—Signal Monitor Enable

Setting Bit 0 high enables the signal monitor block.

AD9627 Datasheet(PDF) 49 Page - Analog Devices

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