AD9627 datasheet(48/77 Pages) AD

48 / 77 page

AD9627

Rev. B | Page 47 of 76

Addr

(Hex)

Name

Bit 7

(MSB)

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

(LSB)

Default

Value

(Hex)

Default

Notes/

Comments

0x117

Signal Monitor

Result

Channel A

(Global)

Signal Monitor Result Channel A[15:8]

Read only

0x118

Signal Monitor

Result

Channel A

(Global)

Open

Signal Monitor Value Channel A[19:16]

Read only

0x119

Signal Monitor

Result

Channel B

(Global)

Signal Monitor Result Channel B[7:0]

Read only

0x11A

Signal Monitor

Result

Channel B

(Global)

Signal Monitor Result Channel B[15:8]

Read only

0x11B

Signal Monitor

Result

Channel B

(Global)

Open

Signal Monitor Result Channel B[19:16]

Read only

MEMORY MAP REGISTER DESCRIPTIONS

For additional information about functions controlled in

Interfacing to High Speed ADCs via SPI.

Sync Control (Register 0x100)

Bit 7—Signal Monitor Sync Enable

Bit 7 enables the sync pulse from the external SYNC input to

the signal monitor block. The sync signal is passed when Bit 7

and Bit 0 are high. This is continuous sync mode.

Bits[6:3]—Reserved

Bit 2—Clock Divider Next Sync Only

If the master sync enable bit (Address 0x100, Bit0) and the clock

divider sync enable bit (Address 0x100, Bit 1) are high, Bit 2 allows

the clock divider to sync to the first sync pulse it receives and to

ignore the rest. The clock divider sync enable bit (Address 0x100,

Bit 1) resets after it syncs.

Bit 1—Clock Divider Sync Enable

Bit 1 gates the sync pulse to the clock divider. The sync signal is

passed when Bit 1 is high and Bit 0 is high. This is continuous

sync mode.

Bit 0—Master Sync Enable

Bit 0 must be high to enable any of the sync functions.

Fast Detect Control (Register 0x104)

Bits[7:4]—Reserved

Bits[3:1]—Fast Detect Mode Select

These bits set the mode of the fast detect output pins (see Table 17).

Bit 0—Fast Detect Enable

Bit 0 is used to enable the fast detect output pins. When the fast

detect output pins are disabled, the outputs go into a high

impedance state. In LVDS mode, when the outputs are

interleaved, the outputs go high-Z only if both channels are

turned off (power-down/standby/output disabled). If only one

channel is turned off (power-down/standby/output disabled), the

fast detect output pins repeat the data of the active channel.

Coarse Upper Threshold (Register 0x105)

Bits[7:3]—Reserved

Bits[2:0]—Coarse Upper Threshold

These bits set the level required to assert the coarse upper

threshold indication (see Table 21).

Fine Upper Threshold (Register 0x106 and Register 0x107)

These registers provide the fine upper limit threshold. This 13-bit

value is compared with the 13-bit magnitude from the ADC block.

If the ADC magnitude exceeds this threshold value, the F_UT

flag is set.

Fine Lower Threshold (Register 0x108 and Register 0x109)

[7:0]

These registers provide the fine lower limit threshold. This 13-bit

value is compared with the 13-bit magnitude from the ADC

block. If the ADC magnitude is less than this threshold value,

the F_LT flag is set.

AD9627 Datasheet(PDF) 48 Page - Analog Devices

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