AD9627 datasheet(7/77 Pages) AD

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AD9627

Rev. B | Page 6 of 76

ADC DC SPECIFICATIONS—AD9627-125/AD9627-150

AVDD = 1.8 V, DVDD = 1.8 V, DRVDD = 3.3 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, DCS

enabled, fast detect output pins disabled, and signal monitor disabled, unless otherwise noted.

Table 2.

Parameter

Temperature

AD9627-125

AD9627-150

Unit

Min

Typ

Max

Min

Typ

Max

RESOLUTION

Full

Bits

ACCURACY

No Missing Codes

Full

Guaranteed

Offset Error

Full

±0.3

±0.6

±0.2

±0.6

% FSR

Gain Error

Full

−0.7

−2.7

−3.9

−0.9

−3.2

−5.2

% FSR

Differential Nonlinearity (DNL)1

Full

±0.4

±0.9

LSB

25°C

±0.2

LSB

Integral Nonlinearity (INL)1

Full

±0.9

±1.3

LSB

25°C

±0.4

±0.5

LSB

MATCHING CHARACTERISTIC

Offset Error

25°C

±0.3

±0.6

±0.2

±0.7

% FSR

Gain Error

25°C

±0.1

±0.75

±0.2

±0.8

% FSR

TEMPERATURE DRIFT

Offset Error

Full

±15

ppm/°C

Gain Error

Full

±95

ppm/°C

INTERNAL VOLTAGE REFERENCE

Output Voltage Error (1 V Mode)

Full

±5

±16

±5

±16

Load Regulation @ 1.0 mA

Full

INPUT REFERRED NOISE

VREF = 1.0 V

25°C

0.3

LSB rms

ANALOG INPUT

Input Span, VREF = 1.0 V

Full

V p-p

Input Capacitance2

Full

VREF INPUT RESISTANCE

Full

kΩ

POWER SUPPLIES

Supply Voltage

AVDD, DVDD

Full

1.7

1.8

1.9

1.7

1.8

1.9

DRVDD (CMOS Mode)

Full

1.7

3.3

3.6

1.7

3.3

3.6

DRVDD (LVDS Mode)

Full

1.7

1.8

1.9

1.7

1.8

1.9

Supply Current

IAVDD1, 3

Full

385

455

419

495

IDVDD1, 3

Full

IDRVDD1 (3.3 V CMOS)

Full

IDRVDD1 (1.8 V CMOS)

Full

IDRVDD1 (1.8 V LVDS)

Full

POWER CONSUMPTION

DC Input

Full

750

800

820

890

Sine Wave Input1 (DRVDD = 1.8 V)

Full

814

895

Sine Wave Input1 (DRVDD = 3.3 V)

Full

900

995

Standby Power4

Full

Power-Down Power

Full

2.5

1 Measured with a low input frequency, full-scale sine wave, with approximately 5 pF loading on each output bit.

2 Input capacitance refers to the effective capacitance between one differential input pin and AGND. See Figure 8 for the equivalent analog input structure.

3 The maximum limit applies to the combination of IAVDD and IDVDD currents.

4 Standby power is measured with a dc input and with the CLK pins inactive (set to AVDD or AGND).

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