AD9627 datasheet(31/77 Pages) AD

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AD9627

Rev. B | Page 30 of 76

In some applications, it may be acceptable to drive the sample

clock inputs with a single-ended CMOS signal. In such applica-

tions, the CLK+ pin should be driven directly from a CMOS gate,

and the CLK− pin should be bypassed to ground with a 0.1 μF

capacitor in parallel with a 39 kΩ resistor (see Figure 60).

CLK+ can be driven directly from a CMOS gate. Although the

CLK+ input circuit supply is AVDD (1.8 V), this input is designed

to withstand input voltages of up to 3.6 V, making the selection

of the drive logic voltage very flexible.

OPTIONAL

100

Ω

0.1µF

39k

Ω

Ω1

150

Ω RESISTOR IS OPTIONAL.

CLK–

CLK+

ADC

AD9627

VCC

Ω

CLOCK

INPUT

AD951x

CMOS DRIVER

Figure 60. Single-Ended 1.8 V CMOS Sample Clock (Up to 150 MSPS)

150

Ω RESISTOR IS OPTIONAL.

OPTIONAL

100

Ω

0.1µF

VCC

Ω1

CLK–

CLK+

ADC

AD9627

Ω

CLOCK

INPUT

AD951x

CMOS DRIVER

Figure 61. Single-Ended 3.3 V CMOS Sample Clock (Up to 150 MSPS)

Input Clock Divider

The AD9627 contains an input clock divider with the ability to

divide the input clock by integer values between 1 and 8. If a

divide ratio other than 1 is selected, the duty cycle stabilizer is

automatically enabled.

The AD9627 clock divider can be synchronized using the external

SYNC input. Bit 1 and Bit 2 of Register 0x100 allow the clock

divider to be resynchronized on every SYNC signal or only on

the first SYNC signal after the register is written. A valid SYNC

causes the clock divider to reset to its initial state. This synchro-

nization feature allows multiple parts to have their clock dividers

aligned to guarantee simultaneous input sampling.

Clock Duty Cycle

Typical high speed ADCs use both clock edges to generate

a variety of internal timing signals and, as a result, may be

sensitive to clock duty cycle. Commonly, a ±5% tolerance is

required on the clock duty cycle to maintain dynamic

performance characteristics.

The AD9627 contains a duty cycle stabilizer (DCS) that retimes

the nonsampling (falling) edge, providing an internal clock

signal with a nominal 50% duty cycle. This allows the user to

provide a wide range of clock input duty cycles without affecting

the performance of the AD9627. Noise and distortion performance

are nearly flat for a wide range of duty cycles with the DCS on,

as shown in Figure 43.

Jitter in the rising edge of the input is still of paramount concern

and is not easily reduced by the internal stabilization circuit.

The duty cycle control loop does not function for clock rates

less than 20 MHz nominally. The loop has a time constant

associated with it thatmust be considered where the clock rate

can change dynamically. A wait time of 1.5 μs to 5 μs is required

after a dynamic clock frequency increase or decrease before the

DCS loop is relocked to the input signal. During the time period

that the loop is not locked, the DCS loop is bypassed, and internal

device timing is dependent on the duty cycle of the input clock

signal. In such applications, it may be appropriate to disable the

duty cycle stabilizer. In all other applications, enabling the DCS

circuit is recommended to maximize ac performance.

Jitter Considerations

High speed, high resolution ADCs are sensitive to the quality

of the clock input. The degradation in SNR from the low

frequency SNR (SNRLF) at a given input frequency (fINPUT) due

to jitter (tJRMS) can be calculated by

SNRHF = −10 log[(2π × fINPUT × tJRMS)2 + 10

)

(

SNR



]

In the equation, the rms aperture jitter represents the clock input

jitter specification. IF undersampling applications are particularly

sensitive to jitter, as illustrated in Figure 62.

100

1000

INPUT FREQUENCY (MHz)

3.00ps

0.05ps

0.20ps

0.5ps

1.0ps

1.50ps

2.00ps

2.50ps

MEASURED

Figure 62. SNR vs. Input Frequency and Jitter

The clock input should be treated as an analog signal in cases

where aperture jitter may affect the dynamic range of the AD9627.

Power supplies for clock drivers should be separated from the

ADC output driver supplies to avoid modulating the clock

signal with digital noise. Low jitter, crystal-controlled oscillators

make the best clock sources. If the clock is generated from another

type of source (by gating, dividing, or another method), it should

be retimed by the original clock at the last step.

Refer to Application Note AN-501 and Application Note AN-756

(see www.analog.com) for more information about jitter perform-

ance as it relates to ADCs.

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